STA/Timing Engineer (Digital PD)
KI-Beschreibung
As a STA/Timing Engineer, you will focus on ensuring high-volume silicon production by developing and validating timing constraints, collaborating with design teams, and enhancing methodologies for static timing analysis.
Anforderungen
3–10 Jahre- •10+ years of experience in the semiconductor industry
- •Minimum 3 years in a technical Digital STA and Timing Signoff role
- •Experience in gathering and defining SDC constraints