Package Design Engineer
KI-Beschreibung
As a Package Design Engineer, you will engage in a variety of tasks, including collaborating with layout engineers and verifying electrical characteristics. This role involves ensuring cost-effective designs and providing support to assembly activities, while keeping the cross-functional team updated on your progress.
Anforderungen
5 Jahre- •Minimum 5 years experience in IC Package Design using Cadence APD
/ SIP - •Hands-on experience using Cadence (Virtuoso
/ Extract IM/ Power DC)/ Ansys SW Tools (SiWave/ Q3D) or similar tools - •Experience using AutoCAD tool