SENIOR DIGITAL / RTL DESIGN ENGINEER(m/w/x)

In this role, you will engage in the full lifecycle of digital IP design, from analyzing specifications to collaborating with various teams, ensuring high-quality results and timely product releases.

Anforderungen

• •B.S./M.S. degree in Electrical Engineering, Physics, Computer Engineering, Information Technology, or related subject with emphasis on hardware design
• •Minimum of 5 years work experience
• •Experience in HDL design, preferably using SystemVerilog
• •Experience with Cadence XCELIUM or comparable simulator
• •Basic knowledge of timing constraints and synthesis
• •Knowledge of functional verification (UVM) and SystemVerilog assertions
• •Knowledge about communication principles and experience with different protocols (UCIe, PCIe, Ethernet, AMBA AXI, or CHI)
• •Experience in scripting (e.g. Python) for automation tasks
• •Hands-on mentality and problem-solving capability
• •Good written and oral communication skills in English