Master Thesis in SmallSat Core Avionics Products: Testing of CCSDS De-/Encoding of Secure F-Series Telecommands/ Telemetry on FPGA(m/w/x)

# Master Thesis in SmallSat Core Avionics Products: Testing of CCSDS De-/Encoding of Secure F-Series Telecommands/ Telemetry on FPGA **Immenstaad am Bodensee** | **Full time** ****Job Description:**** Airbus Defence and Space is looking for a # Master's Student (d/f/m) - Thesis in SmallSat Core Avionics Products: Testing of CCSDS De-/Encoding of Secure F-Series Telecommands/ Telemetry on FPGA You are looking for a master thesis and want to get to know the work of a job title? Then apply now! We look forward to you supporting us in the department designation as a master's student! * Location: Friedrichshafen * Start: 01.09.2025 * Duration: 6 months ****Your location**** At the Airbus site in Friedrichshafen you will be working on innovation where others spend their holidays. Enjoy panoramic views of Lake Constance while having lunch in our canteen. And after work, join one of our many corporate sports groups to go running, sailing or skiing. **Your benefits** * Attractive salary and work-life balance with an 35-hour week (flexitime). * Mobile working after agreement with the department. * Traveling overseas or within Germany (team events) is possible after consultation and agreement from the department. * International environment with the opportunity to network globally. * Work with modern/diversified technologies. * At Airbus, we see you as a valuable team member and you are not hired to brew coffee, instead you are in close contact with the interfaces and are part of our weekly team meetings. * Opportunity to participate in the Generation Airbus Community to expand your own network. ****Your tasks and responsibilities**** * Familiarize with the F-Series secure communications concept. * Familiarize with the CCSDS decoding/encoding standards and already available building blocks. * Integrate/adapt VHDL blocks to assemble a full multi virtual channel communications chain. * Work in the AMD Vivado suite with an IP block design and the hardware description language VHDL for the FPGA. * Develop and execute tests of the downlink chain with hardware in the loop, the satellite simulator and the Mission Control Software * Document the work according to the project templates (MS Word) ****Desired skills and qualifications**** * Enrolled student of aerospace engineering, embedded software/electronics engineering, HW/SW co-design or comparable graduation * Sound knowledge about FPGA programming and VHDL Knowledge in C++ programming * Sound knowledge about embedded systems programming * High level of motivation for learning and improvement of skills, personal initiative and the ability for efficient timing. * Team spirit and willingness to co-operate and working together in an international Company. * Fluent English **Employment Type:** Final-year Thesis ------- **Experience Level:** Student **Job Family:** Stdized Platform, Module & Version Eng. <JF-EN-EL> This job requires an awareness of any potential compliance risks and a commitment to act with integrity, as the foundation for the Company’s success, reputation and sustainable growth. Airbus is committed to achieving workforce diversity and creating an inclusive working environment. We welcome all applications irrespective of social and cultural background, age, gender, disability, sexual orientation or religious belief. Airbus is, and always has been, committed to equal opportunities for all. As such, we will never ask for any type of monetary exchange in the frame of a recruitment process. Any impersonation of Airbus to do so should be reported to emsom@airbus.com. At Airbus, we support you to work, connect and collaborate more easily and flexibly. Wherever possible, we foster flexible working arrangements to stimulate innovative thinking.