Description

You will kickstart your career by designing RTL logic and integrating IP blocks into SoCs. Working with senior experts, you'll ensure design quality through rigorous simulation and timing analysis.

Requirements

• •Degree in Electrical Engineering, Microelectronics, or related
• •Basic understanding of digital logic design
• •Familiarity with Verilog/SystemVerilog or VHDL
• •Basic experience with simulation tools
• •Understanding of CMOS and semiconductor concepts
• •Analytical thinking and attention to detail
• •Fluent written and verbal English skills
• •Academic or internship experience with ASIC/SoC/FPGA
• •Familiarity with Linux development environments
• •Basic scripting knowledge in TCL/Python/Perl/shell
• •Exposure to Synopsys, Cadence, or Siemens EDA
• •Interest in verification or SoC architectures

Tasks

• •Design and implement digital logic blocks using Verilog or SystemVerilog
• •Integrate digital IP blocks into larger SoC designs
• •Develop and maintain testbenches for functional debugging
• •Run simulations and analyze design behavior
• •Resolve RTL issues and support synthesis tasks
• •Perform timing analysis and implementation duties
• •Participate in design reviews and document action items
• •Apply DFT concepts including scan chains and test features
• •Collaborate with senior designers, verification engineers, and architects

Tools & Technologies

Benefits