GF Dresden Mod Two LLC&Co.KG
Junior Mixed‑Signal Memory Circuit Designer(m/w/x)
Full-timeOn-siteJunior
Dresden
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GFGF Dresden Mod Two LLC&Co.KG
Junior Digital Circuit Designer(m/w/x)
Dresden
Full-timeOn-siteJunior
Nejo AI Summary
Designing digital logic blocks for SoC integration at a global semiconductor manufacturer. Familiarity with Verilog/SystemVerilog or VHDL expected. Family friendly part-time models, salary conversion into free time.
Requirements
- Degree in Electrical Engineering, Microelectronics, or related
- Basic understanding of digital logic design
- Familiarity with Verilog/SystemVerilog or VHDL
- Basic experience with simulation tools
- Understanding of CMOS and semiconductor concepts
- Analytical thinking and attention to detail
- Fluent written and verbal English skills
- Academic or internship experience with ASIC/SoC/FPGA
- Familiarity with Linux development environments
- Basic scripting knowledge in TCL/Python/Perl/shell
- Exposure to Synopsys, Cadence, or Siemens EDA
- Interest in verification or SoC architectures
Tasks
- Design and implement digital logic blocks using Verilog or SystemVerilog
- Integrate digital IP blocks into larger SoC designs
- Develop and maintain testbenches for functional debugging
- Run simulations and analyze design behavior
- Resolve RTL issues and support synthesis tasks
- Perform timing analysis and implementation duties
- Participate in design reviews and document action items
- Apply DFT concepts including scan chains and test features
- Collaborate with senior designers, verification engineers, and architects
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- VHDL
- Linux
- TCL
- Python
- Perl
- Synopsys
- Cadence
- Siemens EDA
- ASIC
- SoC
- FPGA
Benefits
Family Support
- Family friendly part-time models
Flexible Working
- Trust flextime
More Vacation Days
- Salary conversion into free time
Bonuses & Incentives
- 13th month salary
- Bonus payments
Other Benefits
- Relocation assistance to Dresden
Career Advancement
- Career stages for every job
Learning & Development
- Internal qualification offers
- External educational qualification promotion
Healthcare & Fitness
- On-site gym
Startup Environment
- Beach volleyball court
Company Bike
- Bike leasing
Free or Subsidized Food
- Subsidized employee restaurant
Informal Culture
- Cooperation at eye level
Team Events
- Budget for team events
Social Impact
- Social commitment via GlobalGives
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of GF Dresden Mod Two LLC&Co.KG and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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GFGF Dresden Mod Two LLC&Co.KG
Junior Digital Circuit Designer(m/w/x)
Dresden
Full-timeOn-siteJunior
Nejo AI Summary
Designing digital logic blocks for SoC integration at a global semiconductor manufacturer. Familiarity with Verilog/SystemVerilog or VHDL expected. Family friendly part-time models, salary conversion into free time.
Requirements
- Degree in Electrical Engineering, Microelectronics, or related
- Basic understanding of digital logic design
- Familiarity with Verilog/SystemVerilog or VHDL
- Basic experience with simulation tools
- Understanding of CMOS and semiconductor concepts
- Analytical thinking and attention to detail
- Fluent written and verbal English skills
- Academic or internship experience with ASIC/SoC/FPGA
- Familiarity with Linux development environments
- Basic scripting knowledge in TCL/Python/Perl/shell
- Exposure to Synopsys, Cadence, or Siemens EDA
- Interest in verification or SoC architectures
Tasks
- Design and implement digital logic blocks using Verilog or SystemVerilog
- Integrate digital IP blocks into larger SoC designs
- Develop and maintain testbenches for functional debugging
- Run simulations and analyze design behavior
- Resolve RTL issues and support synthesis tasks
- Perform timing analysis and implementation duties
- Participate in design reviews and document action items
- Apply DFT concepts including scan chains and test features
- Collaborate with senior designers, verification engineers, and architects
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- VHDL
- Linux
- TCL
- Python
- Perl
- Synopsys
- Cadence
- Siemens EDA
- ASIC
- SoC
- FPGA
Benefits
Family Support
- Family friendly part-time models
Flexible Working
- Trust flextime
More Vacation Days
- Salary conversion into free time
Bonuses & Incentives
- 13th month salary
- Bonus payments
Other Benefits
- Relocation assistance to Dresden
Career Advancement
- Career stages for every job
Learning & Development
- Internal qualification offers
- External educational qualification promotion
Healthcare & Fitness
- On-site gym
Startup Environment
- Beach volleyball court
Company Bike
- Bike leasing
Free or Subsidized Food
- Subsidized employee restaurant
Informal Culture
- Cooperation at eye level
Team Events
- Budget for team events
Social Impact
- Social commitment via GlobalGives
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of GF Dresden Mod Two LLC&Co.KG and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
GF Dresden Mod Two LLC&Co.KG
Industry
Manufacturing
Description
The company is one of the world's leading semiconductor manufacturers, providing innovative process technology solutions.
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