Description

As a Digital Verification Engineer, you will focus on developing verification methodologies and collaborating with designers to validate circuit designs. Your role involves preparing verification plans, managing projects, and utilizing cutting-edge tools to ensure quality.

Requirements

• •Great communication skills
• •Analytical mindset
• •Strong teamwork skills
• •Good scripting techniques
• •Regression setup and management
• •Deep understanding of simulation and verification environments
• •Strong knowledge of metrics-driven verification
• •Deep knowledge of simulation tools and debugging techniques
• •Understanding of verification planning and test bench development
• •Experience with 3rd party VIP usage and test development
• •Experience with Assertion Based Verification
• •5+ years of experience in the semiconductor industry
• •Proven track record in verifying complex designs
• •Skilled in trade-offs between quality and schedule
• •Experience in constrained random test bench development
• •Familiarity with SerDes and high-level protocols
• •Extensive digital verification background
• •Some UVM experience
• •Bachelor of Engineering in Electronics and Electrical Engineering or higher

Tasks

• •Develop design verification methodologies
• •Implement standard debug flows
• •Collaborate with designers on circuit design verification and validation
• •Participate in design reviews
• •Prepare design verification plans based on specifications
• •Plan and schedule projects for timely completion
• •Utilize the latest tools and techniques for design verification
• •Maintain the design verification environment
• •Track and close design bugs