CERN
Mixed-Signal IC Test Engineer(m/w/x)
Full-timeWith HomeofficeExperienced
Genf
from CHF 6,372 - 7,004 / month
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CECERN
Digital IC Design Engineer(m/w/x)
Genf
from CHF 6,372 - 7,004 / month
Full-timeWith Home OfficeExperienced
Nejo AI Summary
Designing RTL for particle accelerator data processing systems. VLSI principles and ASIC/FPGA implementation experience required. 30 days paid leave, comprehensive health insurance.
Requirements
- Digital IC design experience with VLSI principles
- Digital or mixed-signal circuit design/implementation in ASICs/FPGAs
- Digital simulation techniques and tools experience (advantageous)
- RTL design using Verilog/SystemVerilog or VHDL
- Scripting languages (Python, TCL, Shell) and versioning tools (Git) proficiency
- Functional verification methodologies (UVM/SystemVerilog) and simulation tools experience (advantageous)
- Spoken and written English fluency
- Commitment to learn French
- Professional background in Electronics engineering or related field
- Master's degree with 2-6 years post-graduation experience
- PhD with no more than 3 years post-graduation experience
- Never had a CERN fellow or graduate contract before
Tasks
- Conceive and optimize system-level architectures
- Develop data processing strategies
- Design RTL
- Synthesize RTL
- Implement RTL
- Achieve timing closure
- Perform place & route of complex designs
- Contribute to chip signoff
- Perform physical design checks (DRC, LVS, ERC)
- Conduct power integrity analysis
- Participate in formal verification using UVM
- Manage the full RTL-to-GDS flow
- Manage physical signoff with EDA tools
- Collaborate effectively within a multidisciplinary team
- Communicate effectively within a multidisciplinary team
- Share knowledge
- Solve problems
- Achieve results through teamwork
Work Experience
- 2 - 6 years
Education
- Vocational certification
Languages
- English – Native
- French – Basic
Tools & Technologies
- Verilog
- SystemVerilog
- VHDL
- Python
- TCL
- Shell
- Git
- UVM
Benefits
More Vacation Days
- 30 days paid leave
- 2 weeks annual closure
Healthcare & Fitness
- Comprehensive health insurance
Retirement Plans
- CERN Pension Fund membership
Family Support
- Family allowances
Additional Allowances
- Child allowances
- Infant allowances
- Relocation package
- Installation grant
- Travel expenses
Learning & Development
- On-the-job training
- Formal training
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of CERN and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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CECERN
Digital IC Design Engineer(m/w/x)
Genf
from CHF 6,372 - 7,004 / month
Full-timeWith Home OfficeExperienced
Nejo AI Summary
Designing RTL for particle accelerator data processing systems. VLSI principles and ASIC/FPGA implementation experience required. 30 days paid leave, comprehensive health insurance.
Requirements
- Digital IC design experience with VLSI principles
- Digital or mixed-signal circuit design/implementation in ASICs/FPGAs
- Digital simulation techniques and tools experience (advantageous)
- RTL design using Verilog/SystemVerilog or VHDL
- Scripting languages (Python, TCL, Shell) and versioning tools (Git) proficiency
- Functional verification methodologies (UVM/SystemVerilog) and simulation tools experience (advantageous)
- Spoken and written English fluency
- Commitment to learn French
- Professional background in Electronics engineering or related field
- Master's degree with 2-6 years post-graduation experience
- PhD with no more than 3 years post-graduation experience
- Never had a CERN fellow or graduate contract before
Tasks
- Conceive and optimize system-level architectures
- Develop data processing strategies
- Design RTL
- Synthesize RTL
- Implement RTL
- Achieve timing closure
- Perform place & route of complex designs
- Contribute to chip signoff
- Perform physical design checks (DRC, LVS, ERC)
- Conduct power integrity analysis
- Participate in formal verification using UVM
- Manage the full RTL-to-GDS flow
- Manage physical signoff with EDA tools
- Collaborate effectively within a multidisciplinary team
- Communicate effectively within a multidisciplinary team
- Share knowledge
- Solve problems
- Achieve results through teamwork
Work Experience
- 2 - 6 years
Education
- Vocational certification
Languages
- English – Native
- French – Basic
Tools & Technologies
- Verilog
- SystemVerilog
- VHDL
- Python
- TCL
- Shell
- Git
- UVM
Benefits
More Vacation Days
- 30 days paid leave
- 2 weeks annual closure
Healthcare & Fitness
- Comprehensive health insurance
Retirement Plans
- CERN Pension Fund membership
Family Support
- Family allowances
Additional Allowances
- Child allowances
- Infant allowances
- Relocation package
- Installation grant
- Travel expenses
Learning & Development
- On-the-job training
- Formal training
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of CERN and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
CERN
Industry
Research
Description
The company is the European Organisation for Nuclear Research, focusing on probing the fundamental structure of the universe through particle physics.
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