Senior Digital / Rtl Design Engineer(m/w/x)

Anforderungen

• B.S./M.S. degree in Electrical Engineering, Physics, Computer Engineering, Information Technology, or related subject with emphasis on hardware design
• Minimum of 5 years work experience
• Experience in HDL design, preferably using SystemVerilog
• Experience with Cadence XCELIUM or comparable simulator
• Basic knowledge of timing constraints and synthesis
• Knowledge of functional verification (UVM) and SystemVerilog assertions
• Knowledge about communication principles and experience with different protocols (UCIe, PCIe, Ethernet, AMBA AXI, or CHI)
• Experience in scripting (e.g. Python) for automation tasks
• Hands-on mentality and problem-solving capability
• Good written and oral communication skills in English

Aufgaben

• Analyze complex design specifications
• Translate specifications into microarchitecture requirements
• Develop and maintain complex digital IPs at the RTL level
• Own IP blocks or sub-blocks
• Support digital IP blocks from inception to tape out
• Debug errors with the functional verification team
• Create product specification documentation for internal and customer use
• Collaborate with architecture, verification, backend, and firmware teams
• Participate in cross-functional groups for timely product releases

Berufserfahrung

Ausbildung

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