ams OSRAM GmbH
Technical Project Lead - IC Design(m/w/x)
Vollzeitmit HomeofficeSenior
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AMams OSRAM GmbH
Principal Physical Verification Engineer(m/w/x)
Vollzeitmit HomeofficeSenior
Nejo KI-Zusammenfassung
Developing and optimizing Synopsys IC Validator, Siemens Calibre, and Cadence PVS rule decks for physical signoff. Advanced semiconductor manufacturing and IC design fundamentals required. Performance-based bonuses, higher compensation based on expertise.
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Anforderungen
- Bachelor's or Master's Degree in Electrical Engineering, Microelectronics, Semiconductor Physics, Computer Engineering, or related field
- Strong understanding of semiconductor manufacturing and IC design fundamentals, including CMOS technologies, layout methodologies, parasitic effects, reliability, and signoff requirements
- Hands-on experience with Physical Verification tools, especially Synopsys IC Validator (ICV), and familiarity with DRC, LVS, ERC, Antenna, and DFM verification flows
- Programming and automation skills in Python, Tcl, Perl, Shell, or SKILL for developing verification utilities, regression frameworks, and automated workflows
- Strong analytical skills for investigating complex DRC, LVS, ERC, and DFM violations, identifying root causes, and developing effective solutions
- Attention to detail and strong focus on accuracy and consistency
- Ability to work effectively across multidisciplinary teams, supporting design, layout, technology, reliability, and manufacturing groups
- Ability to explain verification findings clearly to layout engineers, circuit designers, CAD teams, and foundry partners
Aufgaben
- Develop and maintain Synopsys IC Validator, Siemens Calibre, and Cadence PVS rule decks for DRC, LVS, ERC, and antenna verification
- Execute physical signoff verification flows using Synopsys IC Validator, Siemens Calibre, and Cadence PVS
- Analyze verification results to ensure tape-out readiness and foundry compliance
- Create and optimize DFM and pattern-matching checks for manufacturability, yield, reliability, and process robustness
- Investigate and resolve complex verification violations through root-cause analysis
- Collaborate with layout engineers, circuit designers, and technology teams to resolve violations
- Develop automation and regression frameworks to improve verification efficiency and rule quality
- Enhance runtime performance and result tracking through automation frameworks
- Support technology qualification and methodology development
- Evaluate new process nodes and validate rule implementations
- Establish golden signoff flows
- Integrate verification results into the overall signoff process
- Ensure a robust and scalable verification methodology
Berufserfahrung
10 Jahre
Ausbildung
Master-Abschluss
Sprachen
Englisch – fließend
Deutsch – Grundkenntnisse
Tools & Technologien
Synopsys IC Validator (ICV)DRCLVSERCAntennaDFMPythonTclPerlShellSKILLCMOS
Benefits
Boni & Prämien
- Additional benefits based on performance, experience and qualification
Attraktive Vergütung
- Higher compensation depending on expertise and skills
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