Dein persönlicher KI-Karriere-Agent
Graduate Engineer – Digital Backend (RTL to GDS), Cadence Flow(m/w/x)
Transforming RTL code into tape-out-ready GDSII databases for embedded semiconductor solutions. Understanding of CMOS, digital design, VLSI, and Verilog/VHDL familiarity essential. Hands-on production ASIC/SoC work, industry-standard EDA tools access.
Anforderungen
- Degree in Electrical, Computer Engineering, or related
- Understanding of CMOS, digital design, and VLSI
- Familiarity with Verilog/VHDL, SDC, and Unix/Linux
- Basic exposure to TCL, Python, or Perl
- Strong analytical thinking and problem-solving skills
- Proactivity, collaboration, and eagerness to learn
- Knowledge of RTL synthesis or P&R concepts
- Understanding of timing analysis or physical verification
- Experience with Cadence, Synopsys, or Mentor
Aufgaben
- Transform RTL code into tape-out-quality GDSII databases
- Execute logic synthesis and generate optimized netlists
- Develop and validate SDC constraints
- Analyze synthesis reports for timing, area, and power
- Collaborate with RTL and verification teams
- Create chip floorplans and macro placements
- Support power grid design and IR-drop-aware placement
- Integrate physical IP and analog blocks
- Manage placement, CTS, and detailed routing
- Optimize designs for timing, congestion, and power
- Implement DFM and power-intent guidelines
- Resolve setup and hold timing violations
- Debug timing paths, parasitics, and cross-talk
- Perform dynamic and static IR-drop analysis
- Validate EM/IR and optimize power delivery networks
- Run DRC, LVS, and ERC layout checks
- Execute ECO cycles and validate final results
- Prepare final tape-out-ready GDSII databases
- Support documentation and sign-off reviews
Ausbildung
- Bachelor-AbschlussODER
- Master-Abschluss
Sprachen
- Englisch – verhandlungssicher
Tools & Technologien
- Verilog
- VHDL
- SDC
- Unix
- Linux
- TCL
- Python
- Perl
- Cadence
- Synopsys
- Mentor
Benefits
Mentoring & Coaching
- Structured onboarding
- Mentorship by Senior Engineers
Sonstige Vorteile
- Hands‑on production ASIC/SoC work
- Tape‑out contribution opportunities
- Global support system
- Employee Resource Groups
Moderne Technikausstattung
- Industry‑standard EDA tools access
Karriere- und Weiterentwicklung
- Career growth path
Startup-Atmosphäre
- Flexible and inclusive environment
Lockere Unternehmenskultur
- People-first culture
Flexibles Arbeiten
- Remote work option
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Graduate Engineer – Digital Backend (RTL to GDS), Cadence Flow(m/w/x)
Transforming RTL code into tape-out-ready GDSII databases for embedded semiconductor solutions. Understanding of CMOS, digital design, VLSI, and Verilog/VHDL familiarity essential. Hands-on production ASIC/SoC work, industry-standard EDA tools access.
Anforderungen
- Degree in Electrical, Computer Engineering, or related
- Understanding of CMOS, digital design, and VLSI
- Familiarity with Verilog/VHDL, SDC, and Unix/Linux
- Basic exposure to TCL, Python, or Perl
- Strong analytical thinking and problem-solving skills
- Proactivity, collaboration, and eagerness to learn
- Knowledge of RTL synthesis or P&R concepts
- Understanding of timing analysis or physical verification
- Experience with Cadence, Synopsys, or Mentor
Aufgaben
- Transform RTL code into tape-out-quality GDSII databases
- Execute logic synthesis and generate optimized netlists
- Develop and validate SDC constraints
- Analyze synthesis reports for timing, area, and power
- Collaborate with RTL and verification teams
- Create chip floorplans and macro placements
- Support power grid design and IR-drop-aware placement
- Integrate physical IP and analog blocks
- Manage placement, CTS, and detailed routing
- Optimize designs for timing, congestion, and power
- Implement DFM and power-intent guidelines
- Resolve setup and hold timing violations
- Debug timing paths, parasitics, and cross-talk
- Perform dynamic and static IR-drop analysis
- Validate EM/IR and optimize power delivery networks
- Run DRC, LVS, and ERC layout checks
- Execute ECO cycles and validate final results
- Prepare final tape-out-ready GDSII databases
- Support documentation and sign-off reviews
Ausbildung
- Bachelor-AbschlussODER
- Master-Abschluss
Sprachen
- Englisch – verhandlungssicher
Tools & Technologien
- Verilog
- VHDL
- SDC
- Unix
- Linux
- TCL
- Python
- Perl
- Cadence
- Synopsys
- Mentor
Benefits
Mentoring & Coaching
- Structured onboarding
- Mentorship by Senior Engineers
Sonstige Vorteile
- Hands‑on production ASIC/SoC work
- Tape‑out contribution opportunities
- Global support system
- Employee Resource Groups
Moderne Technikausstattung
- Industry‑standard EDA tools access
Karriere- und Weiterentwicklung
- Career growth path
Startup-Atmosphäre
- Flexible and inclusive environment
Lockere Unternehmenskultur
- People-first culture
Flexibles Arbeiten
- Remote work option
Gefällt dir diese Stelle?
BetaDein Career Agent findet täglich ähnliche Jobs für dich.
Über das Unternehmen
Renesas Electronics
Branche
Manufacturing
Beschreibung
The company is an embedded semiconductor solution provider offering scalable and comprehensive solutions for various industries.
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