Aumovio
(Senior) ASIC Analog Design Engineer(m/w/x)
Full-timeOn-siteSenior
Frankfurt am Main
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AUAumovio
Digital Design Engineer(m/w/x)
Frankfurt am Main
Full-timeOn-siteExperienced
Nejo AI Summary
Architecting and designing complex digital front-end circuits for autonomous mobility sensors. Deep expertise in ASIC/FPGA design methodologies required. Work on SoC integration with a multidisciplinary team.
Requirements
- Master’s or PhD in Electronics Engineering or related technical field with 4+ years experience, or Bachelor’s degree with 6+ years experience in digital design, SoC integration, or ASIC digital architecture
- Strong proficiency in Verilog, SystemVerilog, or VHDL
- Proven track record of delivering complex digital design projects and collaborating effectively across multidisciplinary teams
- Deep expertise in ASIC and FPGA design methodologies, including front-end architecture and implementation flows
- Working knowledge of UVM
- Strong understanding of digital design flow, including synthesis, simulation, static timing analysis, and related front-end development processes
- Hands-on experience with formal verification tools, such as Siemens Questa Formal and Synopsys Spyglass
- Good understanding of CDC, RDC, and multi-power-domain design techniques
- Experience in µC IPs eg. ARM or RISC-V is a strong plus
- Proficiency with verification simulators (e.g., VCS, Questa, Xcelium)
- Experience with Design for Testability (DFT) and Design for Manufacturing (DFM) practices
- Knowledge of Formal Verification methodologies and tools (e.g., JasperGold, VC Formal)
- Strong scripting experience for automation (Python, Perl, Shell, Tcl)
- Experience with SoC-level verification, emulation, or FPGA prototyping
- Exposure to low-power/UPF verification flows
- Applications from severely handicapped people are welcome
Tasks
- Architect and design complex digital front-end circuits
- Verify FPGA and ASIC implementations
- Define digital design requirements
- Develop architectural specifications
- Code high-quality HDL modules
- Focus on reusability, efficiency, and area-optimized design
- Lead and participate in design reviews
- Provide constructive feedback
- Enhance design robustness and quality
- Apply mixed-signal understanding
- Integrate digital front-end with analog components
- Define optimal system and component-level concepts
- Drive digitization initiatives
- Collaborate with cross-functional teams
- Establish cost-effective solutions
- Meet functional, performance, and architectural objectives
- Provide technical guidance and mentorship
- Contribute to engineering excellence
- Refine digital design methodologies
- Enhance development workflows and toolchains
- Create and maintain comprehensive design documentation
- Develop and execute verification strategies
- Create test plans and document results
- Build SystemVerilog/UVM-based testbenches
- Develop reusable verification components
Work Experience
- 4 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- VHDL
- UVM
- Siemens Questa Formal
- Synopsys Spyglass
- VCS
- Questa
- Xcelium
- Python
- Perl
- Shell
- Tcl
- ARM
- RISC-V
- JasperGold
- VC Formal
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Aumovio and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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AUAumovio
Digital Design Engineer(m/w/x)
Frankfurt am Main
Full-timeOn-siteExperienced
Nejo AI Summary
Architecting and designing complex digital front-end circuits for autonomous mobility sensors. Deep expertise in ASIC/FPGA design methodologies required. Work on SoC integration with a multidisciplinary team.
Requirements
- Master’s or PhD in Electronics Engineering or related technical field with 4+ years experience, or Bachelor’s degree with 6+ years experience in digital design, SoC integration, or ASIC digital architecture
- Strong proficiency in Verilog, SystemVerilog, or VHDL
- Proven track record of delivering complex digital design projects and collaborating effectively across multidisciplinary teams
- Deep expertise in ASIC and FPGA design methodologies, including front-end architecture and implementation flows
- Working knowledge of UVM
- Strong understanding of digital design flow, including synthesis, simulation, static timing analysis, and related front-end development processes
- Hands-on experience with formal verification tools, such as Siemens Questa Formal and Synopsys Spyglass
- Good understanding of CDC, RDC, and multi-power-domain design techniques
- Experience in µC IPs eg. ARM or RISC-V is a strong plus
- Proficiency with verification simulators (e.g., VCS, Questa, Xcelium)
- Experience with Design for Testability (DFT) and Design for Manufacturing (DFM) practices
- Knowledge of Formal Verification methodologies and tools (e.g., JasperGold, VC Formal)
- Strong scripting experience for automation (Python, Perl, Shell, Tcl)
- Experience with SoC-level verification, emulation, or FPGA prototyping
- Exposure to low-power/UPF verification flows
- Applications from severely handicapped people are welcome
Tasks
- Architect and design complex digital front-end circuits
- Verify FPGA and ASIC implementations
- Define digital design requirements
- Develop architectural specifications
- Code high-quality HDL modules
- Focus on reusability, efficiency, and area-optimized design
- Lead and participate in design reviews
- Provide constructive feedback
- Enhance design robustness and quality
- Apply mixed-signal understanding
- Integrate digital front-end with analog components
- Define optimal system and component-level concepts
- Drive digitization initiatives
- Collaborate with cross-functional teams
- Establish cost-effective solutions
- Meet functional, performance, and architectural objectives
- Provide technical guidance and mentorship
- Contribute to engineering excellence
- Refine digital design methodologies
- Enhance development workflows and toolchains
- Create and maintain comprehensive design documentation
- Develop and execute verification strategies
- Create test plans and document results
- Build SystemVerilog/UVM-based testbenches
- Develop reusable verification components
Work Experience
- 4 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- VHDL
- UVM
- Siemens Questa Formal
- Synopsys Spyglass
- VCS
- Questa
- Xcelium
- Python
- Perl
- Shell
- Tcl
- ARM
- RISC-V
- JasperGold
- VC Formal
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Aumovio and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
Aumovio
Industry
Automotive
Description
Das Unternehmen AUMOVIO bietet ein breites Portfolio für sichere, vernetzte und autonome Mobilität, einschließlich Sensorlösungen und Softwareexpertise.
Not a perfect match?
- Aumovio
(Senior) ASIC Analog Design Engineer(m/w/x)
Full-timeOn-siteSeniorFrankfurt am Main - Aumovio
Analog Mixed Signal Design Engineer(m/w/x)
Full-timeOn-siteExperiencedFrankfurt am Main - Aumovio
ASIC Analog Layout Engineer(m/w/x)
Full-timeOn-siteSeniorFrankfurt am Main - Hyundai Motorsport GmbH
Senior Design Engineer – Cooling and Hydraulic Systems(m/w/x)
Full-timeOn-siteSeniorFrankfurt am Main - Vantage Data Centers Germany GmbH
Senior Electrical Engineer(m/w/x)
Full-timeOn-siteSeniorFrankfurt am Main