Description

As a Senior DFT Engineer, you will design and implement innovative test solutions for complex SoCs while collaborating with a skilled team across Europe. This role enhances silicon testability and drives improvements in a dynamic startup environment.

Requirements

• •Minimum of 5 years in DFT engineering
• •SystemVerilog RTL, TCL, Python, Unix/Linux workflows
• •Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, gate-level verification
• •Siemens, Synopsys, or Cadence DFT tool experience
• •Familiarity with IEEE 1149.x / 1500 / 1687 standards, synthesis flow, timing analysis
• •Strong problem-solving skills, collaboration, and passion for semiconductor innovation

Tasks

• •Design test solutions for complex SoCs
• •Implement scan insertion and ATPG
• •Integrate Memory BIST and JTAG/IJTAG flows
• •Conduct fault simulation
• •Collaborate with RTL, verification, and physical design teams
• •Support silicon bring-up and debugging
• •Optimize test coverage and yield
• •Contribute to methodology improvements
• •Share best practices with team members

Tools & Technologies

Benefits