Axelera AI
Processor Verification Engineer(m/w/x)
Full-timeRemoteSenior
Zürich
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Designing test solutions for complex SoCs in next-gen AI platforms, including scan insertion and BIST integration. 5+ years in test design for complex SoCs with Siemens, Synopsys, or Cadence tools required. Cross-functional team collaboration.
Requirements
- Minimum of 5 years in DFT engineering
- SystemVerilog RTL, TCL, Python, Unix/Linux workflows
- Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, gate-level verification
- Siemens, Synopsys, or Cadence DFT tool experience
- Familiarity with IEEE 1149.x / 1500 / 1687 standards, synthesis flow, timing analysis
- Strong problem-solving skills, collaboration, and passion for semiconductor innovation
Tasks
- Design test solutions for complex SoCs
- Implement scan insertion and ATPG
- Integrate Memory BIST and JTAG/IJTAG flows
- Conduct fault simulation
- Collaborate with RTL, verification, and physical design teams
- Support silicon bring-up and debugging
- Optimize test coverage and yield
- Contribute to methodology improvements
- Share best practices with team members
Work Experience
- 5 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Siemens
- Synopsys
- Cadence
Benefits
Competitive Pay
- Attractive compensation package
- Option to get company shares
Retirement Plans
- Pension plan
Healthcare & Fitness
- Extensive employee insurances
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Axelera AI and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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Designing test solutions for complex SoCs in next-gen AI platforms, including scan insertion and BIST integration. 5+ years in test design for complex SoCs with Siemens, Synopsys, or Cadence tools required. Cross-functional team collaboration.
Requirements
- Minimum of 5 years in DFT engineering
- SystemVerilog RTL, TCL, Python, Unix/Linux workflows
- Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, gate-level verification
- Siemens, Synopsys, or Cadence DFT tool experience
- Familiarity with IEEE 1149.x / 1500 / 1687 standards, synthesis flow, timing analysis
- Strong problem-solving skills, collaboration, and passion for semiconductor innovation
Tasks
- Design test solutions for complex SoCs
- Implement scan insertion and ATPG
- Integrate Memory BIST and JTAG/IJTAG flows
- Conduct fault simulation
- Collaborate with RTL, verification, and physical design teams
- Support silicon bring-up and debugging
- Optimize test coverage and yield
- Contribute to methodology improvements
- Share best practices with team members
Work Experience
- 5 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Siemens
- Synopsys
- Cadence
Benefits
Competitive Pay
- Attractive compensation package
- Option to get company shares
Retirement Plans
- Pension plan
Healthcare & Fitness
- Extensive employee insurances
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Axelera AI and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
Axelera AI
Industry
IT
Description
The company is creating the next-generation AI platform to support advancements in humanity and improve the world.
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