Axelera AI
Principal Engineer - Silicon Logical Design(m/w/x)
Full-timeRemoteSenior
Zürich
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RERenesas Electronics
Principal Digital Design Engineer(m/w/x)
Zürich
Full-timeWith Home OfficeSenior
Nejo AI Summary
Defining digital architecture for mixed-signal SoCs and leading RTL development. 10+ years of digital IC and SoC design experience required. Flexible work environment, remote option.
Requirements
- MSc or PhD in Electrical Engineering or related discipline
- 10+ years of digital IC and SoC design experience
- Expert-level RTL design skills in Verilog/SystemVerilog
- Strong SoC architecture, integration, synthesis, timing closure background
- Solid knowledge of low-power design, CDC, reset, DFT
- Hands-on experience with industry-standard EDA tools
- Multiple successful silicon tape-outs
- Fluent English communication skills
- Experience with mixed-signal or power IC design
- Familiarity with embedded CPU subsystems
- Exposure to UVM-based verification environments
- Scripting proficiency in Python or Tcl
- Experience in distributed or cross-site engineering teams
- Prior technical ownership at block or chip level
Tasks
- Define digital architecture for complex mixed-signal SoCs
- Lead design and integration of digital subsystems
- Own RTL development from micro-architecture to silicon
- Drive low-power strategies including clock gating and power domain partitioning
- Collaborate with physical design teams on synthesis and timing closure
- Work with analog/mixed-signal teams on AMS interfaces
- Partner with verification teams on coverage-driven verification
- Support silicon bring-up, debug, and product validation
- Author and review micro-architecture specifications
- Define and enforce RTL coding standards
- Mentor junior and mid-level engineers
- Contribute to IP reuse strategy and design methodology
- Influence product roadmap and direction
Work Experience
- 10 years
Education
- Master's degree
Languages
- English – Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- Synopsys
- Cadence
- ARM Cortex-M
- Python
- Tcl
Benefits
Competitive Pay
- Competitive compensation
Other Benefits
- Comprehensive benefits package
- Employee Resource Groups
Flexible Working
- Flexible work environment
- Remote work option
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Renesas Electronics and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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RERenesas Electronics
Principal Digital Design Engineer(m/w/x)
Zürich
Full-timeWith Home OfficeSenior
Nejo AI Summary
Defining digital architecture for mixed-signal SoCs and leading RTL development. 10+ years of digital IC and SoC design experience required. Flexible work environment, remote option.
Requirements
- MSc or PhD in Electrical Engineering or related discipline
- 10+ years of digital IC and SoC design experience
- Expert-level RTL design skills in Verilog/SystemVerilog
- Strong SoC architecture, integration, synthesis, timing closure background
- Solid knowledge of low-power design, CDC, reset, DFT
- Hands-on experience with industry-standard EDA tools
- Multiple successful silicon tape-outs
- Fluent English communication skills
- Experience with mixed-signal or power IC design
- Familiarity with embedded CPU subsystems
- Exposure to UVM-based verification environments
- Scripting proficiency in Python or Tcl
- Experience in distributed or cross-site engineering teams
- Prior technical ownership at block or chip level
Tasks
- Define digital architecture for complex mixed-signal SoCs
- Lead design and integration of digital subsystems
- Own RTL development from micro-architecture to silicon
- Drive low-power strategies including clock gating and power domain partitioning
- Collaborate with physical design teams on synthesis and timing closure
- Work with analog/mixed-signal teams on AMS interfaces
- Partner with verification teams on coverage-driven verification
- Support silicon bring-up, debug, and product validation
- Author and review micro-architecture specifications
- Define and enforce RTL coding standards
- Mentor junior and mid-level engineers
- Contribute to IP reuse strategy and design methodology
- Influence product roadmap and direction
Work Experience
- 10 years
Education
- Master's degree
Languages
- English – Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- Synopsys
- Cadence
- ARM Cortex-M
- Python
- Tcl
Benefits
Competitive Pay
- Competitive compensation
Other Benefits
- Comprehensive benefits package
- Employee Resource Groups
Flexible Working
- Flexible work environment
- Remote work option
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Renesas Electronics and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
Like this job?
BetaYour Career Agent finds similar jobs for you every day.
About the Company
Renesas Electronics
Industry
Manufacturing
Description
The company is an embedded semiconductor solution provider offering scalable and comprehensive solutions for various industries.
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