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Emulation Engineer, Automotive Robotics(m/w/x)
Infrastructure construction for chiplet-based system validation and multi-chiplet scaling for software development. Expert-level proficiency with ZeBu, Palladium, or Veloce platforms required. Remote work model, high-performance RISC-V CPU environment.
Requirements
- 10+ years of SoC or ASIC experience
- Deep understanding of logic design, verification, and emulation platforms
- Fluency in Verilog, SystemVerilog, C, C++, or SystemC
- Experience with ZeBu, Palladium, or Veloce emulators
- Confidence in architecting DV and emulation environments
- Ability to automate processes
- Collaborative and self-driven nature
- Passion for mentoring junior engineers
- Ability to work cross-functionally
Tasks
- Build infrastructure for chiplet-based system validation
- Scale multi-chiplet emulation for software development
- Support DV and power-performance debug
- Develop testbenches, transactors, and monitors
- Enable high-quality and efficient emulation usage
- Drive functional and performance emulation coverage
- Enable and automate low-level software flows
- Optimize platforms for frequency and resource sharing
- Provide technical support for emulation end-users
- Build scalable emulation flows for SiP chiplets
- Manage AI workloads and system-level power
- Integrate AI engines and RISC-V CPUs
- Manage die-to-die links, PCIe, and UCIe
- Integrate memory controllers into unified platforms
- Align virtual prototyping and power analysis
- Develop full-stack validation solutions
- Execute cross-functional silicon bring-up strategies
- Manage RTL to post-silicon debug
Work Experience
- 10 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- C
- C++
- SystemC
- ZeBu
- Palladium
- Veloce
Benefits
Competitive Pay
- Highly competitive compensation package
Flexible Working
- Remote work
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- TenstorrentFull-timeRemoteSeniorMünchen
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Emulation Engineer, Automotive Robotics(m/w/x)
Infrastructure construction for chiplet-based system validation and multi-chiplet scaling for software development. Expert-level proficiency with ZeBu, Palladium, or Veloce platforms required. Remote work model, high-performance RISC-V CPU environment.
Requirements
- 10+ years of SoC or ASIC experience
- Deep understanding of logic design, verification, and emulation platforms
- Fluency in Verilog, SystemVerilog, C, C++, or SystemC
- Experience with ZeBu, Palladium, or Veloce emulators
- Confidence in architecting DV and emulation environments
- Ability to automate processes
- Collaborative and self-driven nature
- Passion for mentoring junior engineers
- Ability to work cross-functionally
Tasks
- Build infrastructure for chiplet-based system validation
- Scale multi-chiplet emulation for software development
- Support DV and power-performance debug
- Develop testbenches, transactors, and monitors
- Enable high-quality and efficient emulation usage
- Drive functional and performance emulation coverage
- Enable and automate low-level software flows
- Optimize platforms for frequency and resource sharing
- Provide technical support for emulation end-users
- Build scalable emulation flows for SiP chiplets
- Manage AI workloads and system-level power
- Integrate AI engines and RISC-V CPUs
- Manage die-to-die links, PCIe, and UCIe
- Integrate memory controllers into unified platforms
- Align virtual prototyping and power analysis
- Develop full-stack validation solutions
- Execute cross-functional silicon bring-up strategies
- Manage RTL to post-silicon debug
Work Experience
- 10 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- SystemVerilog
- C
- C++
- SystemC
- ZeBu
- Palladium
- Veloce
Benefits
Competitive Pay
- Highly competitive compensation package
Flexible Working
- Remote work
About the Company
Tenstorrent
Industry
IT
Description
Tenstorrent leads in AI technology, revolutionizing performance, ease of use, and cost efficiency with its RISC-V CPU.
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