CERN
Firmware Developer - FPGA(m/w/x)
Full-timeWith HomeofficeExperienced
Genf
from CHF 6,372 - 7,004 / month
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CECERN
Embedded Systems Engineer(m/w/x)
Genf
from CHF 5,266 - 5,793 / month
Full-timeWith Home OfficeExperienced
Nejo AI Summary
Developing FPGA gateware and embedded C for CERN's LHCb detector control systems. FPGA gateware development and C code optimization knowledge required. 30 days paid leave, tax-free stipend.
Requirements
- Knowledge in developing, simulating, and validating FPGA gateware
- Experience in writing, profiling, and optimising C code
- Knowledge in hardware/software specification and co-design
- VHDL 2008 (VUnit and UVVM experience is a plus)
- C for embedded applications and Linux device drivers (Rust is a plus)
- Intel Quartus or AMD Vivado toolchains (both is a plus)
- RISC-V instruction set architecture (experience with FPGA softcores like PicoRV32, Nios® V, Microblaze™ V is a plus)
- Low-level communication interfaces (I2C, JTAG, DDR, ...) (experience with lpGBT is a plus)
- Linux distributions for System-on-Chip FPGAs (Yocto, Petalinux, ...)
- Spoken and written English, with commitment to learn French
- National of a CERN Member or Associate Member State
- Maximum two years of professional experience since graduation in Electronics Engineer (or related field) with Bachelor's or Master's degree
- Never had a CERN fellow or graduate contract before
- Applicants without University degree are not eligible
- Applicants with a PhD are not eligible
Tasks
- Contribute to next-generation readout and control systems for LHCb
- Focus on FPGA gateware and low-level embedded software
- Participate in design, implementation, and testing of high-performance solutions
- Interface with detector electronics and data acquisition systems
- Evolve CERN's distributed control infrastructure
- Collaborate with hardware, firmware, and control system engineers
- Define system requirements and interface specifications
- Analyse detector control workloads for performance benchmarks
- Distribute control functions across FPGA logic and embedded processors
- Optimise performance, reliability, and maintainability
- Test and validate prototypes in laboratory environments
- Prepare clear technical documentation and guidelines
- Support developers and researchers integrating solutions
Education
- Compulsory education
Languages
- English – Native
- French – Basic
Tools & Technologies
- FPGA gateware
- C
- VHDL 2008
- VUnit
- UVVM
- Rust
- Intel Quartus
- AMD Vivado
- RISC-V
- PicoRV32
- Nios® V
- Microblaze™ V
- I2C
- JTAG
- DDR
- lpGBT
- Yocto
- Petalinux
Benefits
Additional Allowances
- Monthly stipend between 5266-5793 Swiss Francs (tax free)
- Family, child and infant monthly allowances
- Relocation package
More Vacation Days
- 30 days paid leave per year
- 2 weeks annual closure
Healthcare & Fitness
- Comprehensive health insurance scheme
Retirement Plans
- CERN Pension Fund membership
Learning & Development
- On-the-job and formal training
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of CERN and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
Not a perfect match?
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CECERN
Embedded Systems Engineer(m/w/x)
Genf
from CHF 5,266 - 5,793 / month
Full-timeWith Home OfficeExperienced
Nejo AI Summary
Developing FPGA gateware and embedded C for CERN's LHCb detector control systems. FPGA gateware development and C code optimization knowledge required. 30 days paid leave, tax-free stipend.
Requirements
- Knowledge in developing, simulating, and validating FPGA gateware
- Experience in writing, profiling, and optimising C code
- Knowledge in hardware/software specification and co-design
- VHDL 2008 (VUnit and UVVM experience is a plus)
- C for embedded applications and Linux device drivers (Rust is a plus)
- Intel Quartus or AMD Vivado toolchains (both is a plus)
- RISC-V instruction set architecture (experience with FPGA softcores like PicoRV32, Nios® V, Microblaze™ V is a plus)
- Low-level communication interfaces (I2C, JTAG, DDR, ...) (experience with lpGBT is a plus)
- Linux distributions for System-on-Chip FPGAs (Yocto, Petalinux, ...)
- Spoken and written English, with commitment to learn French
- National of a CERN Member or Associate Member State
- Maximum two years of professional experience since graduation in Electronics Engineer (or related field) with Bachelor's or Master's degree
- Never had a CERN fellow or graduate contract before
- Applicants without University degree are not eligible
- Applicants with a PhD are not eligible
Tasks
- Contribute to next-generation readout and control systems for LHCb
- Focus on FPGA gateware and low-level embedded software
- Participate in design, implementation, and testing of high-performance solutions
- Interface with detector electronics and data acquisition systems
- Evolve CERN's distributed control infrastructure
- Collaborate with hardware, firmware, and control system engineers
- Define system requirements and interface specifications
- Analyse detector control workloads for performance benchmarks
- Distribute control functions across FPGA logic and embedded processors
- Optimise performance, reliability, and maintainability
- Test and validate prototypes in laboratory environments
- Prepare clear technical documentation and guidelines
- Support developers and researchers integrating solutions
Education
- Compulsory education
Languages
- English – Native
- French – Basic
Tools & Technologies
- FPGA gateware
- C
- VHDL 2008
- VUnit
- UVVM
- Rust
- Intel Quartus
- AMD Vivado
- RISC-V
- PicoRV32
- Nios® V
- Microblaze™ V
- I2C
- JTAG
- DDR
- lpGBT
- Yocto
- Petalinux
Benefits
Additional Allowances
- Monthly stipend between 5266-5793 Swiss Francs (tax free)
- Family, child and infant monthly allowances
- Relocation package
More Vacation Days
- 30 days paid leave per year
- 2 weeks annual closure
Healthcare & Fitness
- Comprehensive health insurance scheme
Retirement Plans
- CERN Pension Fund membership
Learning & Development
- On-the-job and formal training
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of CERN and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
CERN
Industry
Research
Description
The company is the European Organisation for Nuclear Research, focusing on probing the fundamental structure of the universe through particle physics.
Not a perfect match?
- CERN
Firmware Developer - FPGA(m/w/x)
Full-timeWith HomeofficeExperiencedGenffrom CHF 6,372 - 7,004 / month - CERN
Software Engineer - Accelerator Controls(m/w/x)
Full-timeWith HomeofficeExperiencedGenffrom CHF 5,266 - 5,793 / month - CERN
Digital IC Design Engineer(m/w/x)
Full-timeWith HomeofficeExperiencedGenffrom CHF 6,372 - 7,004 / month - CERN
Software Developer for Control Systems(m/w/x)
Full-timeWith HomeofficeJuniorGenffrom CHF 5,266 - 5,793 / month - CERN
Mixed-Signal IC Test Engineer(m/w/x)
Full-timeWith HomeofficeExperiencedGenffrom CHF 6,372 - 7,004 / month