CERN
Firmware Developer - FPGA(m/w/x)
Full-timeWith HomeofficeExperienced
Genf
from CHF 6,372 - 7,004 / month
New Job?Nejo!
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CECERN
Embedded Systems Engineer(m/w/x)
Genf
from CHF 5,266 - 5,793 / month
Full-timeWith Home OfficeJunior
Nejo AI Summary
FPGA gateware and bare-metal embedded software development for CERN's scientific instruments. VHDL 2008 and C optimization experience required. 30 days paid leave, 2-week annual closure.
Requirements
- Knowledge in developing, simulating, validating FPGA gateware
- Experience in writing, profiling, optimising C code
- Knowledge in hardware/software specification and co-design
- VHDL 2008 (VUnit and UVVM experience is a plus)
- C for embedded applications and Linux device drivers (Rust is a plus)
- Intel Quartus or AMD Vivado toolchains (both is a plus)
- RISC-V instruction set architecture (experience with FPGA softcores like PicoRV32, Nios® V, Microblaze™ V is a plus)
- Low-level communication interfaces (I2C, JTAG, DDR, ...) (experience with lpGBT is a plus)
- Linux distributions for System-on-Chip FPGAs (Yocto, Petalinux, ...)
- Spoken and written English, commitment to learn French
- National of a CERN Member or Associate Member State
- Maximum two years professional experience since graduation in Electronics Engineer or related field
- Highest educational qualification is Bachelor's or Master's degree
- Never had a CERN fellow or graduate contract before
- No University degree applicants are eligible
- No PhD applicants are eligible
Tasks
- Contribute to developing readout and control systems
- Focus on FPGA gateware development
- Develop low-level embedded software
- Work in bare-metal environments
- Work in Linux environments
- Design scalable solutions
- Implement high-performance solutions
- Test scalable solutions
- Test high-performance solutions
- Interface with detector electronics
- Interface with data acquisition systems
- Evolve distributed control infrastructure
- Ensure reliable detector system operation
- Ensure efficient detector system operation
- Ensure safe detector system operation
- Collaborate with engineers to define requirements
- Collaborate with engineers to define interface specifications
- Analyze detector control workloads
- Define performance benchmarks
- Implement solutions distributing control functions
- Optimize performance with distributed functions
- Optimize reliability with distributed functions
- Optimize maintainability with distributed functions
- Test prototypes in laboratory environments
- Validate prototypes in laboratory environments
- Refine prototypes in laboratory environments
- Prepare technical documentation
- Prepare technical guidelines
Education
- Compulsory education
Languages
- English – Business Fluent
- French – Basic
Tools & Technologies
- FPGA
- C
- VHDL 2008
- VUnit
- UVVM
- Rust
- Intel Quartus
- AMD Vivado
- RISC-V
- PicoRV32
- Nios® V
- Microblaze™ V
- I2C
- JTAG
- DDR
- lpGBT
- Yocto
- Petalinux
Benefits
More Vacation Days
- 30 days paid leave
- 2 weeks annual closure
Healthcare & Fitness
- Comprehensive health insurance
Retirement Plans
- CERN Pension Fund membership
Family Support
- Family allowances
Other Benefits
- Relocation package
Learning & Development
- On-the-job training
- Formal training
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of CERN and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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CECERN
Embedded Systems Engineer(m/w/x)
Genf
from CHF 5,266 - 5,793 / month
Full-timeWith Home OfficeJunior
Nejo AI Summary
FPGA gateware and bare-metal embedded software development for CERN's scientific instruments. VHDL 2008 and C optimization experience required. 30 days paid leave, 2-week annual closure.
Requirements
- Knowledge in developing, simulating, validating FPGA gateware
- Experience in writing, profiling, optimising C code
- Knowledge in hardware/software specification and co-design
- VHDL 2008 (VUnit and UVVM experience is a plus)
- C for embedded applications and Linux device drivers (Rust is a plus)
- Intel Quartus or AMD Vivado toolchains (both is a plus)
- RISC-V instruction set architecture (experience with FPGA softcores like PicoRV32, Nios® V, Microblaze™ V is a plus)
- Low-level communication interfaces (I2C, JTAG, DDR, ...) (experience with lpGBT is a plus)
- Linux distributions for System-on-Chip FPGAs (Yocto, Petalinux, ...)
- Spoken and written English, commitment to learn French
- National of a CERN Member or Associate Member State
- Maximum two years professional experience since graduation in Electronics Engineer or related field
- Highest educational qualification is Bachelor's or Master's degree
- Never had a CERN fellow or graduate contract before
- No University degree applicants are eligible
- No PhD applicants are eligible
Tasks
- Contribute to developing readout and control systems
- Focus on FPGA gateware development
- Develop low-level embedded software
- Work in bare-metal environments
- Work in Linux environments
- Design scalable solutions
- Implement high-performance solutions
- Test scalable solutions
- Test high-performance solutions
- Interface with detector electronics
- Interface with data acquisition systems
- Evolve distributed control infrastructure
- Ensure reliable detector system operation
- Ensure efficient detector system operation
- Ensure safe detector system operation
- Collaborate with engineers to define requirements
- Collaborate with engineers to define interface specifications
- Analyze detector control workloads
- Define performance benchmarks
- Implement solutions distributing control functions
- Optimize performance with distributed functions
- Optimize reliability with distributed functions
- Optimize maintainability with distributed functions
- Test prototypes in laboratory environments
- Validate prototypes in laboratory environments
- Refine prototypes in laboratory environments
- Prepare technical documentation
- Prepare technical guidelines
Education
- Compulsory education
Languages
- English – Business Fluent
- French – Basic
Tools & Technologies
- FPGA
- C
- VHDL 2008
- VUnit
- UVVM
- Rust
- Intel Quartus
- AMD Vivado
- RISC-V
- PicoRV32
- Nios® V
- Microblaze™ V
- I2C
- JTAG
- DDR
- lpGBT
- Yocto
- Petalinux
Benefits
More Vacation Days
- 30 days paid leave
- 2 weeks annual closure
Healthcare & Fitness
- Comprehensive health insurance
Retirement Plans
- CERN Pension Fund membership
Family Support
- Family allowances
Other Benefits
- Relocation package
Learning & Development
- On-the-job training
- Formal training
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of CERN and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
CERN
Industry
Science
Description
The company is the European Organisation for Nuclear Research, focusing on probing the fundamental structure of the universe through particle physics.
Not a perfect match?
- CERN
Firmware Developer - FPGA(m/w/x)
Full-timeWith HomeofficeExperiencedGenffrom CHF 6,372 - 7,004 / month - CERN
Mixed-Signal IC Test Engineer(m/w/x)
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DevOps Engineer for Data Management(m/w/x)
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Full-Stack Software Engineer(m/w/x)
Full-timeWith HomeofficeExperiencedGenffrom CHF 6,372 - 7,004 / month - CERN
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