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ALALTEN

Digital Verification Engineer – Semiconductor(m/w/x)

München
Full-timeWith Home OfficeExperienced

Verifying mixed-signal designs with formal methods and random-constraint testbenches at engineering service provider. Extensive System Verilog and UVM methodology knowledge required. Bike leasing, mobile working possible.

Requirements

  • Completed engineering degree in electrical engineering, computer science, or similar studies
  • Practical experience in digital functional verification and common safety standards
  • Extensive programming skills in System Verilog and System Verilog assertions
  • Good knowledge of UVM methodology, Specman - e language, scripting languages like Python or Perl, and ability to interpret RTL and Gatelevel code
  • Good communication skills in English
  • Language: English

Tasks

  • Verify mixed-signal designs at block and system levels
  • Interpret product requirements to develop verification concepts
  • Create product verification specifications
  • Perform random-constraint testbenches using state-of-the-art techniques
  • Create assertions to validate designs with formal methods
  • Collaborate with lab and test engineers, designers, system architects, and verification engineers across multiple sites

Work Experience

  • approx. 1 - 4 years

Education

  • Bachelor's degree

Languages

  • EnglishBusiness Fluent

Tools & Technologies

  • System Verilog
  • UVM methodology
  • Specman - e language
  • Python
  • Perl

Benefits

Flexible Working

  • Flexible working hours
  • Mobile working possible

Company Bike

  • Bike leasing

Public Transport Subsidies

  • Reduced travel rates

Team Events

  • Team events
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