Axelera AI
Principal Engineer - Silicon Logical Design(m/w/x)
VollzeitRemoteSenior
Zürich
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RERenesas Electronics
Principal Digital Design Engineer(m/w/x)
Zürich
Vollzeitmit HomeofficeSenior
Nejo KI-Zusammenfassung
Defining digital architecture for mixed-signal SoCs and leading RTL development. 10+ years of digital IC and SoC design experience required. Flexible work environment, remote option.
Anforderungen
- MSc or PhD in Electrical Engineering or related discipline
- 10+ years of digital IC and SoC design experience
- Expert-level RTL design skills in Verilog/SystemVerilog
- Strong SoC architecture, integration, synthesis, timing closure background
- Solid knowledge of low-power design, CDC, reset, DFT
- Hands-on experience with industry-standard EDA tools
- Multiple successful silicon tape-outs
- Fluent English communication skills
- Experience with mixed-signal or power IC design
- Familiarity with embedded CPU subsystems
- Exposure to UVM-based verification environments
- Scripting proficiency in Python or Tcl
- Experience in distributed or cross-site engineering teams
- Prior technical ownership at block or chip level
Aufgaben
- Define digital architecture for complex mixed-signal SoCs
- Lead design and integration of digital subsystems
- Own RTL development from micro-architecture to silicon
- Drive low-power strategies including clock gating and power domain partitioning
- Collaborate with physical design teams on synthesis and timing closure
- Work with analog/mixed-signal teams on AMS interfaces
- Partner with verification teams on coverage-driven verification
- Support silicon bring-up, debug, and product validation
- Author and review micro-architecture specifications
- Define and enforce RTL coding standards
- Mentor junior and mid-level engineers
- Contribute to IP reuse strategy and design methodology
- Influence product roadmap and direction
Berufserfahrung
- 10 Jahre
Ausbildung
- Master-Abschluss
Sprachen
- Englisch – fließend
Tools & Technologien
- Verilog
- SystemVerilog
- Synopsys
- Cadence
- ARM Cortex-M
- Python
- Tcl
Benefits
Attraktive Vergütung
- Competitive compensation
Sonstige Vorteile
- Comprehensive benefits package
- Employee Resource Groups
Flexibles Arbeiten
- Flexible work environment
- Remote work option
Die Originalanzeige dieses Stellenangebotes in der aktuellsten Version findest du hier. Nejo hat diesen Job automatisch von der Website des Unternehmens Renesas Electronics erfasst und die Informationen auf Nejo mit Hilfe von KI für dich aufbereitet. Trotz sorgfältiger Analyse können einzelne Informationen unvollständig oder ungenau sein. Bitte prüfe immer alle Angaben in der Originalanzeige! Inhalte und Urheberrechte der Originalanzeige liegen beim ausschreibenden Unternehmen.
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RERenesas Electronics
Principal Digital Design Engineer(m/w/x)
Zürich
Vollzeitmit HomeofficeSenior
Nejo KI-Zusammenfassung
Defining digital architecture for mixed-signal SoCs and leading RTL development. 10+ years of digital IC and SoC design experience required. Flexible work environment, remote option.
Anforderungen
- MSc or PhD in Electrical Engineering or related discipline
- 10+ years of digital IC and SoC design experience
- Expert-level RTL design skills in Verilog/SystemVerilog
- Strong SoC architecture, integration, synthesis, timing closure background
- Solid knowledge of low-power design, CDC, reset, DFT
- Hands-on experience with industry-standard EDA tools
- Multiple successful silicon tape-outs
- Fluent English communication skills
- Experience with mixed-signal or power IC design
- Familiarity with embedded CPU subsystems
- Exposure to UVM-based verification environments
- Scripting proficiency in Python or Tcl
- Experience in distributed or cross-site engineering teams
- Prior technical ownership at block or chip level
Aufgaben
- Define digital architecture for complex mixed-signal SoCs
- Lead design and integration of digital subsystems
- Own RTL development from micro-architecture to silicon
- Drive low-power strategies including clock gating and power domain partitioning
- Collaborate with physical design teams on synthesis and timing closure
- Work with analog/mixed-signal teams on AMS interfaces
- Partner with verification teams on coverage-driven verification
- Support silicon bring-up, debug, and product validation
- Author and review micro-architecture specifications
- Define and enforce RTL coding standards
- Mentor junior and mid-level engineers
- Contribute to IP reuse strategy and design methodology
- Influence product roadmap and direction
Berufserfahrung
- 10 Jahre
Ausbildung
- Master-Abschluss
Sprachen
- Englisch – fließend
Tools & Technologien
- Verilog
- SystemVerilog
- Synopsys
- Cadence
- ARM Cortex-M
- Python
- Tcl
Benefits
Attraktive Vergütung
- Competitive compensation
Sonstige Vorteile
- Comprehensive benefits package
- Employee Resource Groups
Flexibles Arbeiten
- Flexible work environment
- Remote work option
Die Originalanzeige dieses Stellenangebotes in der aktuellsten Version findest du hier. Nejo hat diesen Job automatisch von der Website des Unternehmens Renesas Electronics erfasst und die Informationen auf Nejo mit Hilfe von KI für dich aufbereitet. Trotz sorgfältiger Analyse können einzelne Informationen unvollständig oder ungenau sein. Bitte prüfe immer alle Angaben in der Originalanzeige! Inhalte und Urheberrechte der Originalanzeige liegen beim ausschreibenden Unternehmen.
Über das Unternehmen
Renesas Electronics
Branche
Manufacturing
Beschreibung
The company is an embedded semiconductor solution provider offering scalable and comprehensive solutions for various industries.
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