Beschreibung

In this role, you will collaborate with a talented team to create efficient verification environments for sensor applications in automotive and industrial markets. Your expertise will drive improvements in workflows and methodologies, ensuring high-quality results.

Anforderungen

• •Master's degree or comparable in electrical engineering, computer engineering, or related field
• •Expert knowledge in functional verification with at least 10 years of specific work experience
• •Expert knowledge in UVM and constrained random verification with regressions
• •At least basic knowledge in formal verification and SystemVerilog assertions
• •State-of-the-art development and management of verification environments, components, and verification IP
• •Knowledge of verification of designs with MCU and hardware/software co-simulation
• •Knowledge related to mixed-signal verification
• •Good documentation skills and willingness to work on documentation in automotive development processes according to standards IATF 16949 and ISO 26262
• •Excellent communication skills and good team player
• •Ability to understand development processes and develop strategies for improvement
• •Ability and attitude to learn new methods and work towards efficient adoption
• •Self-driven work style
• •Work in a multi-site, multi-culture development environment
• •Proven record of technical publications and technical presentations is a plus
• •Fluent English in text and speech

Aufgaben

• •Drive project planning and execution as verification lead
• •Set up complex verification environments and test cases for designs
• •Focus on automotive applications following IATF 16949 standards
• •Develop verification strategies for industrial applications
• •Establish best practices for various verification methodologies
• •Streamline verification strategies to enhance efficiency and meet schedules
• •Collaborate with cross-disciplinary project team members
• •Mentor team members to enhance overall capabilities and efficiency
• •Support the development of quality procedures related to verification
• •Assist in selecting verification IP
• •Evaluate and adopt new tools and workflows for improved verification
• •Provide feedback to enhance existing verification environments

Benefits