You will perform verification tasks for low power and multi-clock domain designs, support RTL designers, and develop infrastructure while working on advanced technology nodes and SoC-level designs.
Anforderungen
- •Willingness to learn new technologies
- •Experience in verification of multi-clock domain designs
- •Some experience with mixed signal systems
- •Experience developing verification infrastructure for SOC designs
- •Experience with UVM
- •Advanced level in Python
- •Advanced level in GIT
- •Experience with Chisel hardware design language (helpful)
- •Experience working beyond standard cell libraries (helpful)
Deine Aufgaben
- •Verify low power, multi-clock domain designs
- •Work on advanced technology nodes
- •Assist RTL designers with functional verification
- •Verify SOC level designs
- •Develop verification infrastructure
Original Beschreibung
## Verification Engineer (IC Design)
###### Permanent employee, Full-time ·Dresden
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##### About the Role
In this role you are responsible for system level and integration verification of the designs, as they are produced by the RTL design team. You will also have to provide feedback during the architecture exploration process for future generation designs. You will work on SOC level designs, within a multi-power domain, and will be responsible for building our verification architecture.
##### What you will do:
* Verification of low power, multi clock domain designs
* Work on advanced technology nodes
* Help RTL designers with module level functional verification
* Verification of SOC level design
* Develop the verification infrastructure
##### What you should bring in:
* Willingness to learn new, potentially unconventional, technologies/techniques
* Experience in verification of multi clock domain designs
* Some experience in working with mixed signal systems
* Experience developing the verification infrastructure for SOC designs
* Experience with UVM
* Advanced level in Python & GIT
##### Helpful but not required:
* Experience with the Chisel hardware design language
* Experience in working with designs beyond the standard cell libraries