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FRFraunhofer-Institut für Integrierte Schaltungen IIS

Working Student - Design of Low-Power Digital systems(m/w/x)

Erlangen
Part-timeWorking StudentOn-site
AI/ML
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Designing low-power RISC-V SoC architectures and IPs for microelectronics research. Digital chip design and SystemVerilog experience required. Flexible working hours and days.

Requirements

  • Master's program in Microelectronics or related field
  • Willingness to learn low-power design methods or experience with UPF, Power Intent Table
  • Practical experience with digital chip design, digital system architectures (RISC-V), SystemVerilog, and EDA tools
  • Excellent German and good English skills
  • Flexibility, reliability, self-reliance, and enthusiasm for new technologies

Tasks

  • Contribute ideas to digital chip design
  • Develop efficient low-power architectures for RISC-V SoCs
  • Support the team in setting up low-power architectures
  • Support the team in analyzing low-power architectures
  • Develop potential IPs related to low power
  • Develop potential processes related to low power
  • Support accelerators
  • Support compression concepts

Education

  • Currently in higher education

Languages

  • German – Native
  • English – Business Fluent

Tools & Technologies

  • UPF
  • Power Intent Table
  • digital chip design
  • digital system architectures
  • RISC-V
  • SystemVerilog
  • EDA tools

Benefits

Flexible Working

  • Flexible working hours
  • Flexible working days

Informal Culture

  • Open and friendly atmosphere

Purpose-Driven Work

  • Valued ideas
  • Application-oriented research
  • Practical knowledge application

Diverse Work

  • Diverse tasks
  • Exciting and pioneering projects

Career Advancement

  • Attractive post-study opportunities

Other Benefits

  • Master's thesis opportunity
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