RANOVUS
Analog ASIC Design Engineer(m/w/x)
Full-timeOn-siteExperienced
Nürnberg
New Job?Nejo!
Your personal AI career agent
FRFraunhofer-Institut für Integrierte Schaltungen IIS
System on Chip (SoC) Verification Engineer(m/w/x)
Erlangen
Full-time, Part-timeOn-site
AI/ML
Nejo AI Summary
Building block/chip level testbenches for RISC-V architectures and low-power designs at research institute for AI/microelectronics. Proven SystemVerilog and UVM verification environment experience required. Career program for female scientists, flexible working hours.
Requirements
- University degree in electrical engineering, IT/computer science, or related field
- Solid understanding of digital logic design and RISC-V-based SoC architecture
- Proven experience with SystemVerilog and UVM-based verification environments
- Very good English and good German language skills
- Proactive and independent mindset
- Familiarity with C/C++ programming, assembly, and object-oriented languages such as Python
- Knowledge of industry-standard interfaces and bus protocols (e.g., AXI)
- Experience with IP verification methods, integration verification specific to RISC-V and embedded CPU verification
- Interest in low power verification techniques and formal verification tools (e.g. JasperGold)
Tasks
- Understand RISC-V architectures and low-power designs
- Build block and chip level testbenches using verification methodologies
- Translate design specifications into verification plans
- Develop and maintain reusable testbenches for IP/block-level verification
- Support IP integration verification
- Create constraint-random and directed test cases for RISC-V SoCs
- Build and analyze coverage models
- Refine tests to close coverage gaps
- Debug test failures and manage bug tracking
- Ensure coverage closure
- Lead verification reviews to maintain coding quality
- Prepare, run, and evaluate regression runs
Education
- Bachelor's degree
Languages
- English – Business Fluent
- German – Advanced
Tools & Technologies
- SystemVerilog
- UVM
- C
- C++
- Python
- JasperGold
Benefits
Informal Culture
- Friendly working atmosphere
- Creative freedom
Learning & Development
- Personal development opportunities
Flexible Working
- Flexible working hours
Career Advancement
- Career program for female scientists
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Fraunhofer-Institut für Integrierte Schaltungen IIS and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
Not a perfect match?
- RANOVUS
ASIC Validation Engineer(m/w/x)
Full-timeOn-siteExperiencedNürnberg - Huawei Research Center Germany & Austria
Hardware Design Engineer(m/w/x)
Full-timeOn-siteExperiencedNürnberg - Fraunhofer-Gesellschaft
Wissenschaftlicher Mitarbeiter - Weiterentwicklung SiC-Technologien(m/w/x)
Full-time/Part-timeTemporary contractOn-siteNot specifiedErlangen - Bertrandt
Entwicklungsingenieur für Mess- und Prüftechnik(m/w/x)
Full-timeOn-siteJuniorHeroldsberg
FRFraunhofer-Institut für Integrierte Schaltungen IIS
System on Chip (SoC) Verification Engineer(m/w/x)
Erlangen
Full-time, Part-timeOn-site
AI/ML
Nejo AI Summary
Building block/chip level testbenches for RISC-V architectures and low-power designs at research institute for AI/microelectronics. Proven SystemVerilog and UVM verification environment experience required. Career program for female scientists, flexible working hours.
Requirements
- University degree in electrical engineering, IT/computer science, or related field
- Solid understanding of digital logic design and RISC-V-based SoC architecture
- Proven experience with SystemVerilog and UVM-based verification environments
- Very good English and good German language skills
- Proactive and independent mindset
- Familiarity with C/C++ programming, assembly, and object-oriented languages such as Python
- Knowledge of industry-standard interfaces and bus protocols (e.g., AXI)
- Experience with IP verification methods, integration verification specific to RISC-V and embedded CPU verification
- Interest in low power verification techniques and formal verification tools (e.g. JasperGold)
Tasks
- Understand RISC-V architectures and low-power designs
- Build block and chip level testbenches using verification methodologies
- Translate design specifications into verification plans
- Develop and maintain reusable testbenches for IP/block-level verification
- Support IP integration verification
- Create constraint-random and directed test cases for RISC-V SoCs
- Build and analyze coverage models
- Refine tests to close coverage gaps
- Debug test failures and manage bug tracking
- Ensure coverage closure
- Lead verification reviews to maintain coding quality
- Prepare, run, and evaluate regression runs
Education
- Bachelor's degree
Languages
- English – Business Fluent
- German – Advanced
Tools & Technologies
- SystemVerilog
- UVM
- C
- C++
- Python
- JasperGold
Benefits
Informal Culture
- Friendly working atmosphere
- Creative freedom
Learning & Development
- Personal development opportunities
Flexible Working
- Flexible working hours
Career Advancement
- Career program for female scientists
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Fraunhofer-Institut für Integrierte Schaltungen IIS and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
Fraunhofer-Institut für Integrierte Schaltungen IIS
Industry
Research
Description
Das Unternehmen ist eines der weltweit führenden Institute für anwendungsorientierte Forschung in den Bereichen Künstliche Intelligenz, Mikroelektronik und Datenerfassung.
Not a perfect match?
- RANOVUS
Analog ASIC Design Engineer(m/w/x)
Full-timeOn-siteExperiencedNürnberg - RANOVUS
ASIC Validation Engineer(m/w/x)
Full-timeOn-siteExperiencedNürnberg - Huawei Research Center Germany & Austria
Hardware Design Engineer(m/w/x)
Full-timeOn-siteExperiencedNürnberg - Fraunhofer-Gesellschaft
Wissenschaftlicher Mitarbeiter - Weiterentwicklung SiC-Technologien(m/w/x)
Full-time/Part-timeTemporary contractOn-siteNot specifiedErlangen - Bertrandt
Entwicklungsingenieur für Mess- und Prüftechnik(m/w/x)
Full-timeOn-siteJuniorHeroldsberg