GEMESYS GmbH
Senior Analog-/Mixed-Signal Design Engineer(m/w/x)
Full-timeWith HomeofficeSenior
Berlin, Bochum
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AXAxelera AI
Senior Silicon Physical Design Engineer(m/w/x)
Berlin
Full-timeRemoteSenior
Nejo AI Summary
Physical design for next-generation AI platform silicon, including synthesis, floorplanning, and EMIR signoff. 10+ years in physical design (RTL to GDS) and hands-on EDA tool expertise required. Option to get company shares.
Requirements
- 10+ years of experience in Physical Design (RTL to GDS)
- Strong communication and teamwork skills
- Expertise in all aspects of physical design
- Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre)
- Proficiency in clocking techniques and CTS
- Experience in IP integration across various domains
- Strong scripting skills (Python and Tcl)
- Proven problem-solving and debugging capabilities
- Fluent in English (spoken and written)
- Experience in floorplanning and top level integration
- Knowledge of chip-package-board co-simulation and packaging
- Experience working with EDA vendors to resolve tool issues
- Understanding of semiconductor device physics and multi-domain design
Tasks
- Perform synthesis, floorplanning, and place and route
- Conduct extraction and timing analysis
- Execute physical verification and EMIR signoff
- Generate constraints and optimize timing
- Implement clock tree synthesis and custom clock-building techniques
- Integrate IPs including memories, I/Os, and embedded processors
- Utilize EDA tools like Primetime, StarRC, and Design Compiler
- Develop automation scripts in Python, Tcl, and Bash
- Debug and resolve technical challenges in physical design
- Collaborate with architecture, RTL, and verification teams
Work Experience
- 10 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Primetime
- StarRC
- Genus
- Innovus
- Design Compiler
- ICC/ICC2
- FC
- Redhawk
- Calibre
- Python
- Tcl
Benefits
Competitive Pay
- Attractive compensation package
- Option to get company shares
Retirement Plans
- Pension plan
Healthcare & Fitness
- Extensive employee insurances
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Axelera AI and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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AXAxelera AI
Senior Silicon Physical Design Engineer(m/w/x)
Berlin
Full-timeRemoteSenior
Nejo AI Summary
Physical design for next-generation AI platform silicon, including synthesis, floorplanning, and EMIR signoff. 10+ years in physical design (RTL to GDS) and hands-on EDA tool expertise required. Option to get company shares.
Requirements
- 10+ years of experience in Physical Design (RTL to GDS)
- Strong communication and teamwork skills
- Expertise in all aspects of physical design
- Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre)
- Proficiency in clocking techniques and CTS
- Experience in IP integration across various domains
- Strong scripting skills (Python and Tcl)
- Proven problem-solving and debugging capabilities
- Fluent in English (spoken and written)
- Experience in floorplanning and top level integration
- Knowledge of chip-package-board co-simulation and packaging
- Experience working with EDA vendors to resolve tool issues
- Understanding of semiconductor device physics and multi-domain design
Tasks
- Perform synthesis, floorplanning, and place and route
- Conduct extraction and timing analysis
- Execute physical verification and EMIR signoff
- Generate constraints and optimize timing
- Implement clock tree synthesis and custom clock-building techniques
- Integrate IPs including memories, I/Os, and embedded processors
- Utilize EDA tools like Primetime, StarRC, and Design Compiler
- Develop automation scripts in Python, Tcl, and Bash
- Debug and resolve technical challenges in physical design
- Collaborate with architecture, RTL, and verification teams
Work Experience
- 10 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Primetime
- StarRC
- Genus
- Innovus
- Design Compiler
- ICC/ICC2
- FC
- Redhawk
- Calibre
- Python
- Tcl
Benefits
Competitive Pay
- Attractive compensation package
- Option to get company shares
Retirement Plans
- Pension plan
Healthcare & Fitness
- Extensive employee insurances
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Axelera AI and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
Axelera AI
Industry
IT
Description
The company is creating the next-generation AI platform to support advancements in humanity and improve the world.
Not a perfect match?
- GEMESYS GmbH
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Senior Backend Engineer Electrical Engineering(m/w/x)
Full-time/Part-timeRemoteSeniorKöln, Aachen, Bonn, Berlin, München, Castrop-Rauxel - Enpal B.V.
Senior Software Engineer - Energy Data Platform(m/w/x)
Full-timeWith HomeofficeSeniorBerlin