Description

In this role, you will be at the forefront of developing advanced multi-core in-memory compute SoCs, engaging in tasks from synthesis to physical verification while collaborating with various teams to ensure project success.

Requirements

• •10+ years of experience in Physical Design (RTL to GDS)
• •Strong communication and teamwork skills
• •Expertise in all aspects of physical design
• •Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre)
• •Proficiency in clocking techniques and CTS
• •Experience in IP integration across various domains
• •Strong scripting skills (Python and Tcl)
• •Proven problem-solving and debugging capabilities
• •Fluent in English (spoken and written)
• •Experience in floorplanning and top level integration
• •Knowledge of chip-package-board co-simulation and packaging
• •Experience working with EDA vendors to resolve tool issues
• •Understanding of semiconductor device physics and multi-domain design

Tasks

• •Perform synthesis, floorplanning, and place and route
• •Conduct extraction and timing analysis
• •Execute physical verification and EMIR signoff
• •Generate constraints and optimize timing
• •Implement clock tree synthesis and custom clock-building techniques
• •Integrate IPs including memories, I/Os, and embedded processors
• •Utilize EDA tools like Primetime, StarRC, and Design Compiler
• •Develop automation scripts in Python, Tcl, and Bash
• •Debug and resolve technical challenges in physical design
• •Collaborate with architecture, RTL, and verification teams

Tools & Technologies

Benefits