EXTOLL GmbH
Senior Functional Verification Engineer(m/w/x)
Full-timeWith HomeofficeSenior
Mannheim, Villach
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EXEXTOLL GmbH
Senior Digital / Rtl Design Engineer(m/w/x)
Mannheim, Villach
Full-timeWith Home OfficeSenior
Nejo AI Summary
Developing complex digital IP blocks for high-speed SerDes chips. 5+ years in HDL design with SystemVerilog and Cadence XCELIUM experience required. Above-average vacation, workation opportunity.
Requirements
- B.S./M.S. degree in Electrical Engineering, Physics, Computer Engineering, Information Technology, or related subject with emphasis on hardware design
- Minimum of 5 years work experience
- Experience in HDL design, preferably using SystemVerilog
- Experience with Cadence XCELIUM or comparable simulator
- Basic knowledge of timing constraints and synthesis
- Knowledge of functional verification (UVM) and SystemVerilog assertions
- Knowledge about communication principles and experience with different protocols (UCIe, PCIe, Ethernet, AMBA AXI, or CHI)
- Experience in scripting (e.g. Python) for automation tasks
- Hands-on mentality and problem-solving capability
- Good written and oral communication skills in English
Tasks
- Analyze complex design specifications
- Translate specifications into microarchitecture requirements
- Develop and maintain complex digital IPs at the RTL level
- Own IP blocks or sub-blocks
- Support digital IP blocks from inception to tape out
- Debug errors with the functional verification team
- Create product specification documentation for internal and customer use
- Collaborate with architecture, verification, backend, and firmware teams
- Participate in cross-functional groups for timely product releases
Work Experience
- 5 years
Education
- Bachelor's degree
Languages
- English – Business Fluent
- German – Basic
Tools & Technologies
- SystemVerilog
- Cadence XCELIUM
- Python
Benefits
Flexible Working
- Flexible work hours
- Working time account
More Vacation Days
- Above-average vacation
Other Benefits
- Mobile working
Workation & Sabbatical
- Workation opportunity
Team Events
- Employee events
Mentorship & Coaching
- Career development support
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of EXTOLL GmbH and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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EXEXTOLL GmbH
Senior Digital / Rtl Design Engineer(m/w/x)
Mannheim, Villach
Full-timeWith Home OfficeSenior
Nejo AI Summary
Developing complex digital IP blocks for high-speed SerDes chips. 5+ years in HDL design with SystemVerilog and Cadence XCELIUM experience required. Above-average vacation, workation opportunity.
Requirements
- B.S./M.S. degree in Electrical Engineering, Physics, Computer Engineering, Information Technology, or related subject with emphasis on hardware design
- Minimum of 5 years work experience
- Experience in HDL design, preferably using SystemVerilog
- Experience with Cadence XCELIUM or comparable simulator
- Basic knowledge of timing constraints and synthesis
- Knowledge of functional verification (UVM) and SystemVerilog assertions
- Knowledge about communication principles and experience with different protocols (UCIe, PCIe, Ethernet, AMBA AXI, or CHI)
- Experience in scripting (e.g. Python) for automation tasks
- Hands-on mentality and problem-solving capability
- Good written and oral communication skills in English
Tasks
- Analyze complex design specifications
- Translate specifications into microarchitecture requirements
- Develop and maintain complex digital IPs at the RTL level
- Own IP blocks or sub-blocks
- Support digital IP blocks from inception to tape out
- Debug errors with the functional verification team
- Create product specification documentation for internal and customer use
- Collaborate with architecture, verification, backend, and firmware teams
- Participate in cross-functional groups for timely product releases
Work Experience
- 5 years
Education
- Bachelor's degree
Languages
- English – Business Fluent
- German – Basic
Tools & Technologies
- SystemVerilog
- Cadence XCELIUM
- Python
Benefits
Flexible Working
- Flexible work hours
- Working time account
More Vacation Days
- Above-average vacation
Other Benefits
- Mobile working
Workation & Sabbatical
- Workation opportunity
Team Events
- Employee events
Mentorship & Coaching
- Career development support
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of EXTOLL GmbH and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
EXTOLL GmbH
Industry
IT
Description
Das Unternehmen ist führend in den Bereichen High-Speed Serializer-Deserializer (SerDes) IP und Interconnect-Technologien für Halbleiterchips.
Not a perfect match?
- EXTOLL GmbH
Senior Functional Verification Engineer(m/w/x)
Full-timeWith HomeofficeSeniorMannheim, Villach - EXTOLL GmbH
Senior Physical Design Engineer(m/w/x)
Full-timeWith HomeofficeSeniorMannheim, Villach - EXTOLL GmbH
Staff / Principal Analog / Mixed-signal Design Engineer(m/w/x)
Full-timeRemoteManagementMannheim, Villach - ABB AG
R&D Engineer – Assembly(m/w/x)
Full-timeWith HomeofficeSeniorMannheim - ABB AG
R&D Embedded Test Engineer(m/w/x)
Full-timeWith HomeofficeExperiencedHeidelberg