Fraunhofer-Institut für Integrierte Schaltungen IIS
Senior Backend Engineer(m/w/x)
Full-time/Part-timeTemporary contractWith HomeofficeSenior
Erlangen
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FRFraunhofer-Institut für Integrierte Schaltungen IIS
Senior Backend Engineer – ASIC / Physical Design(m/w/x)
Erlangen
Full-time, Part-timeWith Home OfficeSenior
AI/ML
Nejo AI Summary
RTL-to-GDSII implementation for ASICs and chiplets, ensuring sign-off quality. 5+ years backend/physical design experience required. Work on cutting-edge semiconductor projects.
Requirements
- Degree in electrical engineering, computer science, or comparable qualification
- At least 5 years relevant professional experience in backend/physical design
- Very good knowledge of Cadence design flow (Genus, Innovus, Tempus)
- Very good knowledge of Siemens EDA (Calibre)
- Solid experience with advanced technology nodes
- Preferred knowledge and hands-on experience in Design for Test (DFT)
- Confident use of common EDA tools
- Scripting experience (Tcl, Python)
- Structured working style
- Analytical working style
- Team-oriented working style
- High degree of independence
- High quality awareness
- Business-fluent English
- German at A1 level
Tasks
- Own RTL-to-GDSII implementation for ASICs, SoCs, and chiplets
- Ensure sign-off-quality results for digital backend implementation
- Perform synthesis, floorplanning, place & route, and Clock Tree Synthesis (CTS)
- Conduct timing closure analyses
- Optimize for performance, power, and area (PPA)
- Work with state-of-the-art technology nodes (e.g., FinFET, GAAFET)
- Collaborate closely with frontend, DFT, and verification teams
- Contribute to the integration of complete system solutions
- Support the tape-out process through design reviews
- Perform technical alignment for tape-out
- Create structured documentation for tape-out
Work Experience
- 5 years
Education
- Vocational certificationOR
- Bachelor's degree
Languages
- English – Business Fluent
- German – Basic
Tools & Technologies
- Cadence design flow
- Genus
- Innovus
- Tempus
- Siemens EDA
- Calibre
- Design for Test
- scan
- ATPG
- boundary scan
- EDA tools
- Tcl
- Python
Benefits
Diverse Work
- Diverse and challenging work
- Projects with practical components
- Work on cutting-edge semiconductor projects
Informal Culture
- Positive and supportive work culture
Mentorship & Coaching
- Structured onboarding process
- Coaching
Flexible Working
- Flexible working hours
- Hybrid work
Learning & Development
- Professional development seminars
- Personal development seminars
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Fraunhofer-Institut für Integrierte Schaltungen IIS and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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FRFraunhofer-Institut für Integrierte Schaltungen IIS
Senior Backend Engineer – ASIC / Physical Design(m/w/x)
Erlangen
Full-time, Part-timeWith Home OfficeSenior
AI/ML
Nejo AI Summary
RTL-to-GDSII implementation for ASICs and chiplets, ensuring sign-off quality. 5+ years backend/physical design experience required. Work on cutting-edge semiconductor projects.
Requirements
- Degree in electrical engineering, computer science, or comparable qualification
- At least 5 years relevant professional experience in backend/physical design
- Very good knowledge of Cadence design flow (Genus, Innovus, Tempus)
- Very good knowledge of Siemens EDA (Calibre)
- Solid experience with advanced technology nodes
- Preferred knowledge and hands-on experience in Design for Test (DFT)
- Confident use of common EDA tools
- Scripting experience (Tcl, Python)
- Structured working style
- Analytical working style
- Team-oriented working style
- High degree of independence
- High quality awareness
- Business-fluent English
- German at A1 level
Tasks
- Own RTL-to-GDSII implementation for ASICs, SoCs, and chiplets
- Ensure sign-off-quality results for digital backend implementation
- Perform synthesis, floorplanning, place & route, and Clock Tree Synthesis (CTS)
- Conduct timing closure analyses
- Optimize for performance, power, and area (PPA)
- Work with state-of-the-art technology nodes (e.g., FinFET, GAAFET)
- Collaborate closely with frontend, DFT, and verification teams
- Contribute to the integration of complete system solutions
- Support the tape-out process through design reviews
- Perform technical alignment for tape-out
- Create structured documentation for tape-out
Work Experience
- 5 years
Education
- Vocational certificationOR
- Bachelor's degree
Languages
- English – Business Fluent
- German – Basic
Tools & Technologies
- Cadence design flow
- Genus
- Innovus
- Tempus
- Siemens EDA
- Calibre
- Design for Test
- scan
- ATPG
- boundary scan
- EDA tools
- Tcl
- Python
Benefits
Diverse Work
- Diverse and challenging work
- Projects with practical components
- Work on cutting-edge semiconductor projects
Informal Culture
- Positive and supportive work culture
Mentorship & Coaching
- Structured onboarding process
- Coaching
Flexible Working
- Flexible working hours
- Hybrid work
Learning & Development
- Professional development seminars
- Personal development seminars
- Language classes
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Fraunhofer-Institut für Integrierte Schaltungen IIS and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
About the Company
Fraunhofer-Institut für Integrierte Schaltungen IIS
Industry
Research
Description
Das Unternehmen ist eines der weltweit führenden Institute für anwendungsorientierte Forschung in den Bereichen Künstliche Intelligenz, Mikroelektronik und Datenerfassung.
Not a perfect match?
- Fraunhofer-Institut für Integrierte Schaltungen IIS
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Hardwareentwickler Leistungselektronik(m/w/x)
Full-timeWith HomeofficeSeniorNürnberg - Fraunhofer-Institut für Integrierte Schaltungen IIS
Mixed-Signal IC Designer – Neuromorphic Computing(m/w/x)
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Full-timeRemoteSeniorNürnberg