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AU
Aumovio
2d ago

ASIC Digital Backend Engineer(m/w/x)

Frankfurt am Main
Full-timeOn-siteExperienced

Description

You will transform RTL code into robust digital layouts, managing everything from synthesis to signoff analysis to ensure ASICs meet critical timing and area goals.

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Requirements

  • Degree in Electrical Engineering, Microelectronics, Physics, or comparable qualification
  • Several years of relevant work experience
  • Knowledge of Cadence physical implementation tools
  • Experience in circuit timing closure strategy
  • Experience with asynchronous clocks and clock-domain crossing
  • Knowledge of deep sub-micron technologies
  • Knowledge of digital circuit design
  • Experience in analog layout as a plus
  • Very good English language skills
  • Teamwork, communication, and negotiation skills
  • Customer focus and anticipation of needs
  • Motivation, integrity, and dynamism

Education

Bachelor's degree

Tasks

  • Understand specifications and RTL design
  • Create design implementation constraints
  • Perform RTL synthesis and DFT insertion
  • Partition the design and execute floor planning
  • Place blocks and ports effectively
  • Analyze route congestion
  • Optimize clock tree, placement, and routing
  • Perform timing and signoff analysis
  • Generate robust, DRC-compliant digital block layouts
  • Meet specific timing and area requirements

Tools & Technologies

CadenceGenusInnovusTempus

Languages

EnglishBusiness Fluent

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