Monolithic Power Systems, Inc. (MPS)
Sr Layout Engineer(m/w/x)
Full-timeOn-siteSenior
Schaffhausen
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MOMonolithic Power Systems, Inc. (MPS)
Sr Digital Design Engineer(m/w/x)
Schaffhausen
Full-timeOn-siteSenior
Nejo AI Summary
End-to-end design of digital and mixed-signal ICs for power delivery architectures. RTL Verilog or System Verilog coding skills required. Design and verification IP integration.
Requirements
- BSEE + 8 years digital ASIC design experience
- MSEE + 5 years digital ASIC design experience
- Independent work and team collaboration
- Solid knowledge of full ASIC development process
- Excellent RTL Verilog or System Verilog coding skills
- Knowledge of System Verilog and UVM verification languages
- Knowledge of verification metrics
- Very good understanding of backend flow
- Very good understanding of Synthesis, P&R, DFT, Power, LEC, STA
- Excellent written/verbal communication skills
- Strong teamwork and collaboration skills
- Knowledge of automotive standards
- Experience with embedded designs
- Experience with firmware development
- Knowledge of power management industry/applications
- Knowledge of I2C, I3C, SPI, USB, PMBUS
- FPGA design and validation experience
- Experience with ARM designs
- Scripting and automation languages (TCL, Python, C/C++)
- Valid disability certificate
Tasks
- Lead end-to-end design and development of digital and mixed-signal ICs
- Define and document digital architecture
- Design, debug, and verify RTL
- Analyze verification metrics
- Define, develop, integrate, and verify IP
- Define and debug synthesis constraints
- Analyze synthesis results and reports
- Define and debug LEC constraints
- Analyze LEC results and reports
- Support P&R with MMMC definition and debugging
- Implement, debug, and analyze DFT
- Generate and simulate ATPG
- Perform gate-level verification
- Conduct power simulations and analysis
- Analyze and sign off timing
- Support AMS verification
- Provide post-silicon validation support
- Interact closely with other departments for product definition
Work Experience
- 5 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- System Verilog
- UVM
- TCL
- Python
- C/C++
- I2C
- I3C
- SPI
- USB
- PMBUS
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Monolithic Power Systems, Inc. (MPS) and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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MOMonolithic Power Systems, Inc. (MPS)
Sr Digital Design Engineer(m/w/x)
Schaffhausen
Full-timeOn-siteSenior
Nejo AI Summary
End-to-end design of digital and mixed-signal ICs for power delivery architectures. RTL Verilog or System Verilog coding skills required. Design and verification IP integration.
Requirements
- BSEE + 8 years digital ASIC design experience
- MSEE + 5 years digital ASIC design experience
- Independent work and team collaboration
- Solid knowledge of full ASIC development process
- Excellent RTL Verilog or System Verilog coding skills
- Knowledge of System Verilog and UVM verification languages
- Knowledge of verification metrics
- Very good understanding of backend flow
- Very good understanding of Synthesis, P&R, DFT, Power, LEC, STA
- Excellent written/verbal communication skills
- Strong teamwork and collaboration skills
- Knowledge of automotive standards
- Experience with embedded designs
- Experience with firmware development
- Knowledge of power management industry/applications
- Knowledge of I2C, I3C, SPI, USB, PMBUS
- FPGA design and validation experience
- Experience with ARM designs
- Scripting and automation languages (TCL, Python, C/C++)
- Valid disability certificate
Tasks
- Lead end-to-end design and development of digital and mixed-signal ICs
- Define and document digital architecture
- Design, debug, and verify RTL
- Analyze verification metrics
- Define, develop, integrate, and verify IP
- Define and debug synthesis constraints
- Analyze synthesis results and reports
- Define and debug LEC constraints
- Analyze LEC results and reports
- Support P&R with MMMC definition and debugging
- Implement, debug, and analyze DFT
- Generate and simulate ATPG
- Perform gate-level verification
- Conduct power simulations and analysis
- Analyze and sign off timing
- Support AMS verification
- Provide post-silicon validation support
- Interact closely with other departments for product definition
Work Experience
- 5 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- System Verilog
- UVM
- TCL
- Python
- C/C++
- I2C
- I3C
- SPI
- USB
- PMBUS
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Monolithic Power Systems, Inc. (MPS) and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
Like this job?
BetaYour Career Agent finds similar jobs for you every day.
About the Company
Monolithic Power Systems, Inc. (MPS)
Industry
Manufacturing
Description
The company is one of the fastest growing in the Semiconductor industry, leading in Integrated Power Semiconductors and Systems Power delivery architectures.
Not a perfect match?
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