GF Europe Sales & Support GmbH
Experienced Application Engineer(m/w/x)
Full-timeWith HomeofficeExperienced
München
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RERenesas Electronics
Graduate Engineer – Digital Backend (RTL to GDS), Cadence Flow(m/w/x)
München
Full-timeWith Home Office
Nejo AI Summary
Transforming RTL code into tape-out-ready GDSII databases for embedded semiconductor solutions. Understanding of CMOS, digital design, VLSI, and Verilog/VHDL familiarity essential. Hands-on production ASIC/SoC work, industry-standard EDA tools access.
Requirements
- Degree in Electrical, Computer Engineering, or related
- Understanding of CMOS, digital design, and VLSI
- Familiarity with Verilog/VHDL, SDC, and Unix/Linux
- Basic exposure to TCL, Python, or Perl
- Strong analytical thinking and problem-solving skills
- Proactivity, collaboration, and eagerness to learn
- Knowledge of RTL synthesis or P&R concepts
- Understanding of timing analysis or physical verification
- Experience with Cadence, Synopsys, or Mentor
Tasks
- Transform RTL code into tape-out-quality GDSII databases
- Execute logic synthesis and generate optimized netlists
- Develop and validate SDC constraints
- Analyze synthesis reports for timing, area, and power
- Collaborate with RTL and verification teams
- Create chip floorplans and macro placements
- Support power grid design and IR-drop-aware placement
- Integrate physical IP and analog blocks
- Manage placement, CTS, and detailed routing
- Optimize designs for timing, congestion, and power
- Implement DFM and power-intent guidelines
- Resolve setup and hold timing violations
- Debug timing paths, parasitics, and cross-talk
- Perform dynamic and static IR-drop analysis
- Validate EM/IR and optimize power delivery networks
- Run DRC, LVS, and ERC layout checks
- Execute ECO cycles and validate final results
- Prepare final tape-out-ready GDSII databases
- Support documentation and sign-off reviews
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- VHDL
- SDC
- Unix
- Linux
- TCL
- Python
- Perl
- Cadence
- Synopsys
- Mentor
Benefits
Mentorship & Coaching
- Structured onboarding
- Mentorship by Senior Engineers
Other Benefits
- Hands‑on production ASIC/SoC work
- Tape‑out contribution opportunities
- Global support system
- Employee Resource Groups
Modern Equipment
- Industry‑standard EDA tools access
Career Advancement
- Career growth path
Startup Environment
- Flexible and inclusive environment
Informal Culture
- People-first culture
Flexible Working
- Remote work option
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Renesas Electronics and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
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RERenesas Electronics
Graduate Engineer – Digital Backend (RTL to GDS), Cadence Flow(m/w/x)
München
Full-timeWith Home Office
Nejo AI Summary
Transforming RTL code into tape-out-ready GDSII databases for embedded semiconductor solutions. Understanding of CMOS, digital design, VLSI, and Verilog/VHDL familiarity essential. Hands-on production ASIC/SoC work, industry-standard EDA tools access.
Requirements
- Degree in Electrical, Computer Engineering, or related
- Understanding of CMOS, digital design, and VLSI
- Familiarity with Verilog/VHDL, SDC, and Unix/Linux
- Basic exposure to TCL, Python, or Perl
- Strong analytical thinking and problem-solving skills
- Proactivity, collaboration, and eagerness to learn
- Knowledge of RTL synthesis or P&R concepts
- Understanding of timing analysis or physical verification
- Experience with Cadence, Synopsys, or Mentor
Tasks
- Transform RTL code into tape-out-quality GDSII databases
- Execute logic synthesis and generate optimized netlists
- Develop and validate SDC constraints
- Analyze synthesis reports for timing, area, and power
- Collaborate with RTL and verification teams
- Create chip floorplans and macro placements
- Support power grid design and IR-drop-aware placement
- Integrate physical IP and analog blocks
- Manage placement, CTS, and detailed routing
- Optimize designs for timing, congestion, and power
- Implement DFM and power-intent guidelines
- Resolve setup and hold timing violations
- Debug timing paths, parasitics, and cross-talk
- Perform dynamic and static IR-drop analysis
- Validate EM/IR and optimize power delivery networks
- Run DRC, LVS, and ERC layout checks
- Execute ECO cycles and validate final results
- Prepare final tape-out-ready GDSII databases
- Support documentation and sign-off reviews
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- Verilog
- VHDL
- SDC
- Unix
- Linux
- TCL
- Python
- Perl
- Cadence
- Synopsys
- Mentor
Benefits
Mentorship & Coaching
- Structured onboarding
- Mentorship by Senior Engineers
Other Benefits
- Hands‑on production ASIC/SoC work
- Tape‑out contribution opportunities
- Global support system
- Employee Resource Groups
Modern Equipment
- Industry‑standard EDA tools access
Career Advancement
- Career growth path
Startup Environment
- Flexible and inclusive environment
Informal Culture
- People-first culture
Flexible Working
- Remote work option
Find the original job posting in its most current version here. Nejo automatically captured this job from the website of Renesas Electronics and processed the information on Nejo with the help of AI for you. Despite careful analysis, some information may be incomplete or inaccurate. Please always verify all details in the original posting! Content and copyrights of the original posting belong to the advertising company.
Like this job?
BetaYour Career Agent finds similar jobs for you every day.
About the Company
Renesas Electronics
Industry
Manufacturing
Description
The company is an embedded semiconductor solution provider offering scalable and comprehensive solutions for various industries.
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