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Digital Verification Engineer – Semiconductor(m/w/x)
Verifying mixed-signal designs with formal methods and random-constraint testbenches at engineering service provider. Extensive System Verilog and UVM methodology knowledge required. Bike leasing, mobile working possible.
Requirements
- Completed engineering degree in electrical engineering, computer science, or similar studies
- Practical experience in digital functional verification and common safety standards
- Extensive programming skills in System Verilog and System Verilog assertions
- Good knowledge of UVM methodology, Specman - e language, scripting languages like Python or Perl, and ability to interpret RTL and Gatelevel code
- Good communication skills in English
- Language: English
Tasks
- Verify mixed-signal designs at block and system levels
- Interpret product requirements to develop verification concepts
- Create product verification specifications
- Perform random-constraint testbenches using state-of-the-art techniques
- Create assertions to validate designs with formal methods
- Collaborate with lab and test engineers, designers, system architects, and verification engineers across multiple sites
Work Experience
- approx. 1 - 4 years
Education
- Bachelor's degree
Languages
- English – Business Fluent
Tools & Technologies
- System Verilog
- UVM methodology
- Specman - e language
- Python
- Perl
Benefits
Flexible Working
- Flexible working hours
- Mobile working possible
Company Bike
- Bike leasing
Public Transport Subsidies
- Reduced travel rates
Team Events
- Team events
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Digital Verification Engineer – Semiconductor(m/w/x)
Verifying mixed-signal designs with formal methods and random-constraint testbenches at engineering service provider. Extensive System Verilog and UVM methodology knowledge required. Bike leasing, mobile working possible.
Requirements
- Completed engineering degree in electrical engineering, computer science, or similar studies
- Practical experience in digital functional verification and common safety standards
- Extensive programming skills in System Verilog and System Verilog assertions
- Good knowledge of UVM methodology, Specman - e language, scripting languages like Python or Perl, and ability to interpret RTL and Gatelevel code
- Good communication skills in English
- Language: English
Tasks
- Verify mixed-signal designs at block and system levels
- Interpret product requirements to develop verification concepts
- Create product verification specifications
- Perform random-constraint testbenches using state-of-the-art techniques
- Create assertions to validate designs with formal methods
- Collaborate with lab and test engineers, designers, system architects, and verification engineers across multiple sites
Work Experience
- approx. 1 - 4 years
Education
- Bachelor's degree
Languages
- English – Business Fluent
Tools & Technologies
- System Verilog
- UVM methodology
- Specman - e language
- Python
- Perl
Benefits
Flexible Working
- Flexible working hours
- Mobile working possible
Company Bike
- Bike leasing
Public Transport Subsidies
- Reduced travel rates
Team Events
- Team events
Like this job?
BetaYour Career Agent finds similar jobs for you every day.
About the Company
ALTEN
Industry
Engineering
Description
The company is one of the world’s leading engineering service providers, committed to shaping the future through innovative solutions.
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