GEMESYS GmbH
Senior Analog-/Mixed-Signal Design Engineer(m/w/x)
Vollzeitmit HomeofficeSenior
Berlin, Bochum
Neuer Job?Nejo!
Dein persönlicher KI-Karriere-Agent
AXAxelera AI
Senior Silicon Physical Design Engineer(m/w/x)
Berlin
VollzeitRemoteSenior
Nejo KI-Zusammenfassung
Physical design for next-generation AI platform silicon, including synthesis, floorplanning, and EMIR signoff. 10+ years in physical design (RTL to GDS) and hands-on EDA tool expertise required. Option to get company shares.
Anforderungen
- 10+ years of experience in Physical Design (RTL to GDS)
- Strong communication and teamwork skills
- Expertise in all aspects of physical design
- Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre)
- Proficiency in clocking techniques and CTS
- Experience in IP integration across various domains
- Strong scripting skills (Python and Tcl)
- Proven problem-solving and debugging capabilities
- Fluent in English (spoken and written)
- Experience in floorplanning and top level integration
- Knowledge of chip-package-board co-simulation and packaging
- Experience working with EDA vendors to resolve tool issues
- Understanding of semiconductor device physics and multi-domain design
Aufgaben
- Perform synthesis, floorplanning, and place and route
- Conduct extraction and timing analysis
- Execute physical verification and EMIR signoff
- Generate constraints and optimize timing
- Implement clock tree synthesis and custom clock-building techniques
- Integrate IPs including memories, I/Os, and embedded processors
- Utilize EDA tools like Primetime, StarRC, and Design Compiler
- Develop automation scripts in Python, Tcl, and Bash
- Debug and resolve technical challenges in physical design
- Collaborate with architecture, RTL, and verification teams
Berufserfahrung
- 10 Jahre
Ausbildung
- Bachelor-AbschlussODER
- Master-Abschluss
Sprachen
- Englisch – verhandlungssicher
Tools & Technologien
- Primetime
- StarRC
- Genus
- Innovus
- Design Compiler
- ICC/ICC2
- FC
- Redhawk
- Calibre
- Python
- Tcl
Benefits
Attraktive Vergütung
- Attractive compensation package
- Option to get company shares
Betriebliche Altersvorsorge
- Pension plan
Gesundheits- & Fitnessangebote
- Extensive employee insurances
Die Originalanzeige dieses Stellenangebotes in der aktuellsten Version findest du hier. Nejo hat diesen Job automatisch von der Website des Unternehmens Axelera AI erfasst und die Informationen auf Nejo mit Hilfe von KI für dich aufbereitet. Trotz sorgfältiger Analyse können einzelne Informationen unvollständig oder ungenau sein. Bitte prüfe immer alle Angaben in der Originalanzeige! Inhalte und Urheberrechte der Originalanzeige liegen beim ausschreibenden Unternehmen.
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AXAxelera AI
Senior Silicon Physical Design Engineer(m/w/x)
Berlin
VollzeitRemoteSenior
Nejo KI-Zusammenfassung
Physical design for next-generation AI platform silicon, including synthesis, floorplanning, and EMIR signoff. 10+ years in physical design (RTL to GDS) and hands-on EDA tool expertise required. Option to get company shares.
Anforderungen
- 10+ years of experience in Physical Design (RTL to GDS)
- Strong communication and teamwork skills
- Expertise in all aspects of physical design
- Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre)
- Proficiency in clocking techniques and CTS
- Experience in IP integration across various domains
- Strong scripting skills (Python and Tcl)
- Proven problem-solving and debugging capabilities
- Fluent in English (spoken and written)
- Experience in floorplanning and top level integration
- Knowledge of chip-package-board co-simulation and packaging
- Experience working with EDA vendors to resolve tool issues
- Understanding of semiconductor device physics and multi-domain design
Aufgaben
- Perform synthesis, floorplanning, and place and route
- Conduct extraction and timing analysis
- Execute physical verification and EMIR signoff
- Generate constraints and optimize timing
- Implement clock tree synthesis and custom clock-building techniques
- Integrate IPs including memories, I/Os, and embedded processors
- Utilize EDA tools like Primetime, StarRC, and Design Compiler
- Develop automation scripts in Python, Tcl, and Bash
- Debug and resolve technical challenges in physical design
- Collaborate with architecture, RTL, and verification teams
Berufserfahrung
- 10 Jahre
Ausbildung
- Bachelor-AbschlussODER
- Master-Abschluss
Sprachen
- Englisch – verhandlungssicher
Tools & Technologien
- Primetime
- StarRC
- Genus
- Innovus
- Design Compiler
- ICC/ICC2
- FC
- Redhawk
- Calibre
- Python
- Tcl
Benefits
Attraktive Vergütung
- Attractive compensation package
- Option to get company shares
Betriebliche Altersvorsorge
- Pension plan
Gesundheits- & Fitnessangebote
- Extensive employee insurances
Die Originalanzeige dieses Stellenangebotes in der aktuellsten Version findest du hier. Nejo hat diesen Job automatisch von der Website des Unternehmens Axelera AI erfasst und die Informationen auf Nejo mit Hilfe von KI für dich aufbereitet. Trotz sorgfältiger Analyse können einzelne Informationen unvollständig oder ungenau sein. Bitte prüfe immer alle Angaben in der Originalanzeige! Inhalte und Urheberrechte der Originalanzeige liegen beim ausschreibenden Unternehmen.
Über das Unternehmen
Axelera AI
Branche
IT
Beschreibung
The company is creating the next-generation AI platform to support advancements in humanity and improve the world.
Noch nicht perfekt?
- GEMESYS GmbH
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