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Physical Design Engineer for Integrated Circuits(m/w/x)
RTL-to-Gate Level synthesis and timing constraint for MCU SoCs. Static Timing Analysis and clock tree implementation expertise required. Close collaboration with design front-end teams.
Requirements
- RTL-to-Gate Level synthesis
- Constraining of circuit timing
- Interface to design front-end for constraint review and RTL changes
- Static Timing Analysis (STA)
- Clock tree implementation and analysis
- Low power consumption optimization
- Floor-planning and manual layout knowledge
- Signal integrity and IR drop analysis and issue fixing
- TCL, Pearl, or Python knowledge
- UNIX / Linux environment experience
- Bachelor or Master degree in Electrical Engineering or similar
- Fluent English
- Ability to work in international teams
- Practical experience in chip design or CAD
- Excellent communication and presentation skills
- Collaborative skills for efficient teamwork
Tasks
- Perform RTL-to-Gate Level synthesis
- Constrain circuit timing
- Interface with the design front-end
- Review design constraints
- Suggest RTL changes for timing-critical paths
- Perform Static Timing Analysis (STA)
- Implement clock trees
- Analyze clock trees
- Optimize for low power consumption
- Perform floor-planning
- Execute manual layout
- Analyze signal integrity and IR drop
- Fix signal integrity and IR drop issues
Work Experience
- approx. 1 - 4 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- TCL
- Pearl
- Python
- UNIX
- Linux
- CAD
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Physical Design Engineer for Integrated Circuits(m/w/x)
RTL-to-Gate Level synthesis and timing constraint for MCU SoCs. Static Timing Analysis and clock tree implementation expertise required. Close collaboration with design front-end teams.
Requirements
- RTL-to-Gate Level synthesis
- Constraining of circuit timing
- Interface to design front-end for constraint review and RTL changes
- Static Timing Analysis (STA)
- Clock tree implementation and analysis
- Low power consumption optimization
- Floor-planning and manual layout knowledge
- Signal integrity and IR drop analysis and issue fixing
- TCL, Pearl, or Python knowledge
- UNIX / Linux environment experience
- Bachelor or Master degree in Electrical Engineering or similar
- Fluent English
- Ability to work in international teams
- Practical experience in chip design or CAD
- Excellent communication and presentation skills
- Collaborative skills for efficient teamwork
Tasks
- Perform RTL-to-Gate Level synthesis
- Constrain circuit timing
- Interface with the design front-end
- Review design constraints
- Suggest RTL changes for timing-critical paths
- Perform Static Timing Analysis (STA)
- Implement clock trees
- Analyze clock trees
- Optimize for low power consumption
- Perform floor-planning
- Execute manual layout
- Analyze signal integrity and IR drop
- Fix signal integrity and IR drop issues
Work Experience
- approx. 1 - 4 years
Education
- Bachelor's degreeOR
- Master's degree
Languages
- English – Business Fluent
Tools & Technologies
- TCL
- Pearl
- Python
- UNIX
- Linux
- CAD
Like this job?
BetaYour Career Agent finds similar jobs for you every day.
About the Company
NXP Semiconductors Germany GmbH
Industry
Engineering
Description
The company drives vehicle connectivity and energy efficiency, developing solutions for the vehicles of tomorrow.
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