Senior Engineer – Verification(m/w/x)

Beschreibung

You will ensure the quality of complex digital designs by developing advanced verification strategies and collaborating with global teams to drive technical excellence and mentor junior engineers.

Anforderungen

• •Degree in Electrical or Computer Engineering
• •8-10 years ASIC/FPGA verification experience
• •Expertise in UVM and SystemVerilog Assertions
• •Understanding of digital design and simulation
• •Scripting experience for automation
• •Excellent problem-solving and analytical skills
• •Ability to work collaboratively
• •Experience mentoring and developing engineering talent
• •Excellent written and verbal English communication
• •Experience with mixed-signal verification
• •Familiarity with major vendor EDA tools
• •Knowledge of PCIe, Ethernet, and USB
• •Experience in safety-critical domains (plus)

Aufgaben

• •Develop and maintain verification plans for digital designs
• •Implement environments for mixed-signal designs
• •Collaborate with global design and architecture teams
• •Debug failures to identify and resolve root causes
• •Drive adoption of UVM and assertion-based verification
• •Define coverage metrics for design functionality
• •Review and approve test plans and coverage reports
• •Mentor junior engineers on technical best practices
• •Evaluate new tools to improve verification efficiency
• •Provide expert feedback during design reviews
• •Communicate project risks and results to stakeholders

Tools & Technologien

Benefits