Beschreibung

As a Digital Verification Engineer, you will engage in verifying mixed-signal designs and interpreting product requirements to shape verification concepts. This role involves creating testbenches and assertions while collaborating with a diverse team across various locations.

Anforderungen

• •Completed engineering degree in electrical engineering, computer science, or similar studies
• •Practical experience in digital functional verification and common safety standards
• •Extensive programming skills in System Verilog and System Verilog assertions
• •Good knowledge of UVM methodology, Specman - e language, scripting languages like Python or Perl, and ability to interpret RTL and Gatelevel code
• •Good communication skills in English
• •Language: English

Aufgaben

• •Verify mixed-signal designs at block and system levels
• •Interpret product requirements to develop verification concepts
• •Create product verification specifications
• •Perform random-constraint testbenches using state-of-the-art techniques
• •Create assertions to validate designs with formal methods
• •Collaborate with lab and test engineers, designers, system architects, and verification engineers across multiple sites

Tools & Technologien

Benefits