Dein persönlicher KI-Karriere-Agent
Digital IC Design Engineer(m/w/x)
Designing RTL for particle accelerator data processing systems. VLSI principles and ASIC/FPGA implementation experience required. 30 days paid leave, comprehensive health insurance.
Anforderungen
- Digital IC design experience with VLSI principles
- Digital or mixed-signal circuit design/implementation in ASICs/FPGAs
- Digital simulation techniques and tools experience (advantageous)
- RTL design using Verilog/SystemVerilog or VHDL
- Scripting languages (Python, TCL, Shell) and versioning tools (Git) proficiency
- Functional verification methodologies (UVM/SystemVerilog) and simulation tools experience (advantageous)
- Spoken and written English fluency
- Commitment to learn French
- Professional background in Electronics engineering or related field
- Master's degree with 2-6 years post-graduation experience
- PhD with no more than 3 years post-graduation experience
- Never had a CERN fellow or graduate contract before
Aufgaben
- Conceive and optimize system-level architectures
- Develop data processing strategies
- Design RTL
- Synthesize RTL
- Implement RTL
- Achieve timing closure
- Perform place & route of complex designs
- Contribute to chip signoff
- Perform physical design checks (DRC, LVS, ERC)
- Conduct power integrity analysis
- Participate in formal verification using UVM
- Manage the full RTL-to-GDS flow
- Manage physical signoff with EDA tools
- Collaborate effectively within a multidisciplinary team
- Communicate effectively within a multidisciplinary team
- Share knowledge
- Solve problems
- Achieve results through teamwork
Berufserfahrung
- 2 - 6 Jahre
Ausbildung
- Abgeschlossene Berufsausbildung
Sprachen
- Englisch – fließend
- Französisch – Grundkenntnisse
Tools & Technologien
- Verilog
- SystemVerilog
- VHDL
- Python
- TCL
- Shell
- Git
- UVM
Benefits
Mehr Urlaubstage
- 30 days paid leave
- 2 weeks annual closure
Gesundheits- & Fitnessangebote
- Comprehensive health insurance
Betriebliche Altersvorsorge
- CERN Pension Fund membership
Familienfreundlichkeit
- Family allowances
Sonstige Zulagen
- Child allowances
- Infant allowances
- Relocation package
- Installation grant
- Travel expenses
Weiterbildungsangebote
- On-the-job training
- Formal training
- Language classes
Noch nicht perfekt?
- CERNVollzeitmit HomeofficeBerufserfahrenGenfab CHF 6.372 - 7.004 / Monat
- CERN
Firmware Developer - FPGA(m/w/x)
Vollzeitmit HomeofficeBerufserfahrenGenfab CHF 6.372 - 7.004 / Monat - CERN
Embedded Systems Engineer(m/w/x)
Vollzeitmit HomeofficeJuniorGenfab CHF 5.266 - 5.793 / Monat - CERN
Big Data Software Engineer(m/w/x)
Vollzeitmit HomeofficeBerufserfahrenGenf - CERN
High-Performance Compute (HPC) Engineer(m/w/x)
Vollzeitmit HomeofficeBerufserfahrenGenf
Digital IC Design Engineer(m/w/x)
Designing RTL for particle accelerator data processing systems. VLSI principles and ASIC/FPGA implementation experience required. 30 days paid leave, comprehensive health insurance.
Anforderungen
- Digital IC design experience with VLSI principles
- Digital or mixed-signal circuit design/implementation in ASICs/FPGAs
- Digital simulation techniques and tools experience (advantageous)
- RTL design using Verilog/SystemVerilog or VHDL
- Scripting languages (Python, TCL, Shell) and versioning tools (Git) proficiency
- Functional verification methodologies (UVM/SystemVerilog) and simulation tools experience (advantageous)
- Spoken and written English fluency
- Commitment to learn French
- Professional background in Electronics engineering or related field
- Master's degree with 2-6 years post-graduation experience
- PhD with no more than 3 years post-graduation experience
- Never had a CERN fellow or graduate contract before
Aufgaben
- Conceive and optimize system-level architectures
- Develop data processing strategies
- Design RTL
- Synthesize RTL
- Implement RTL
- Achieve timing closure
- Perform place & route of complex designs
- Contribute to chip signoff
- Perform physical design checks (DRC, LVS, ERC)
- Conduct power integrity analysis
- Participate in formal verification using UVM
- Manage the full RTL-to-GDS flow
- Manage physical signoff with EDA tools
- Collaborate effectively within a multidisciplinary team
- Communicate effectively within a multidisciplinary team
- Share knowledge
- Solve problems
- Achieve results through teamwork
Berufserfahrung
- 2 - 6 Jahre
Ausbildung
- Abgeschlossene Berufsausbildung
Sprachen
- Englisch – fließend
- Französisch – Grundkenntnisse
Tools & Technologien
- Verilog
- SystemVerilog
- VHDL
- Python
- TCL
- Shell
- Git
- UVM
Benefits
Mehr Urlaubstage
- 30 days paid leave
- 2 weeks annual closure
Gesundheits- & Fitnessangebote
- Comprehensive health insurance
Betriebliche Altersvorsorge
- CERN Pension Fund membership
Familienfreundlichkeit
- Family allowances
Sonstige Zulagen
- Child allowances
- Infant allowances
- Relocation package
- Installation grant
- Travel expenses
Weiterbildungsangebote
- On-the-job training
- Formal training
- Language classes
Über das Unternehmen
CERN
Branche
Research
Beschreibung
The company is the European Organisation for Nuclear Research, focusing on probing the fundamental structure of the universe through particle physics.
Noch nicht perfekt?
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Firmware Developer - FPGA(m/w/x)
Vollzeitmit HomeofficeBerufserfahrenGenfab CHF 6.372 - 7.004 / Monat - CERN
Embedded Systems Engineer(m/w/x)
Vollzeitmit HomeofficeJuniorGenfab CHF 5.266 - 5.793 / Monat - CERN
Big Data Software Engineer(m/w/x)
Vollzeitmit HomeofficeBerufserfahrenGenf - CERN
High-Performance Compute (HPC) Engineer(m/w/x)
Vollzeitmit HomeofficeBerufserfahrenGenf