Dein persönlicher KI-Karriere-Agent
Physical Design Engineer for Integrated Circuits(m/w/x)
RTL-to-Gate Level synthesis and timing constraint for MCU SoCs. Static Timing Analysis and clock tree implementation expertise required. Close collaboration with design front-end teams.
Anforderungen
- RTL-to-Gate Level synthesis
- Constraining of circuit timing
- Interface to design front-end for constraint review and RTL changes
- Static Timing Analysis (STA)
- Clock tree implementation and analysis
- Low power consumption optimization
- Floor-planning and manual layout knowledge
- Signal integrity and IR drop analysis and issue fixing
- TCL, Pearl, or Python knowledge
- UNIX / Linux environment experience
- Bachelor or Master degree in Electrical Engineering or similar
- Fluent English
- Ability to work in international teams
- Practical experience in chip design or CAD
- Excellent communication and presentation skills
- Collaborative skills for efficient teamwork
Aufgaben
- Perform RTL-to-Gate Level synthesis
- Constrain circuit timing
- Interface with the design front-end
- Review design constraints
- Suggest RTL changes for timing-critical paths
- Perform Static Timing Analysis (STA)
- Implement clock trees
- Analyze clock trees
- Optimize for low power consumption
- Perform floor-planning
- Execute manual layout
- Analyze signal integrity and IR drop
- Fix signal integrity and IR drop issues
Berufserfahrung
- ca. 1 - 4 Jahre
Ausbildung
- Bachelor-AbschlussODER
- Master-Abschluss
Sprachen
- Englisch – verhandlungssicher
Tools & Technologien
- TCL
- Pearl
- Python
- UNIX
- Linux
- CAD
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Physical Design Engineer for Integrated Circuits(m/w/x)
RTL-to-Gate Level synthesis and timing constraint for MCU SoCs. Static Timing Analysis and clock tree implementation expertise required. Close collaboration with design front-end teams.
Anforderungen
- RTL-to-Gate Level synthesis
- Constraining of circuit timing
- Interface to design front-end for constraint review and RTL changes
- Static Timing Analysis (STA)
- Clock tree implementation and analysis
- Low power consumption optimization
- Floor-planning and manual layout knowledge
- Signal integrity and IR drop analysis and issue fixing
- TCL, Pearl, or Python knowledge
- UNIX / Linux environment experience
- Bachelor or Master degree in Electrical Engineering or similar
- Fluent English
- Ability to work in international teams
- Practical experience in chip design or CAD
- Excellent communication and presentation skills
- Collaborative skills for efficient teamwork
Aufgaben
- Perform RTL-to-Gate Level synthesis
- Constrain circuit timing
- Interface with the design front-end
- Review design constraints
- Suggest RTL changes for timing-critical paths
- Perform Static Timing Analysis (STA)
- Implement clock trees
- Analyze clock trees
- Optimize for low power consumption
- Perform floor-planning
- Execute manual layout
- Analyze signal integrity and IR drop
- Fix signal integrity and IR drop issues
Berufserfahrung
- ca. 1 - 4 Jahre
Ausbildung
- Bachelor-AbschlussODER
- Master-Abschluss
Sprachen
- Englisch – verhandlungssicher
Tools & Technologien
- TCL
- Pearl
- Python
- UNIX
- Linux
- CAD
Gefällt dir diese Stelle?
BetaDein Career Agent findet täglich ähnliche Jobs für dich.
Über das Unternehmen
NXP Semiconductors Germany GmbH
Branche
Engineering
Beschreibung
The company drives vehicle connectivity and energy efficiency, developing solutions for the vehicles of tomorrow.
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