Beschreibung

As a Formal Verification Engineer, you will focus on developing verification methodologies, participating in design reviews, and ensuring project timelines are met. This role involves collaborating with engineers to enhance efficiency through optimized verification models.

Anforderungen

• •Great communication skills
• •Analytical mindset
• •Strong teamwork skills
• •Good scripting techniques (Python, Perl, or TCL)
• •Deep understanding of Formal Verification technologies
• •Strong knowledge of metrics-driven verification
• •Proficiency in temporal logic assertion-based languages (SVA or PSL)
• •Knowledge of traditional simulation-based verification methodologies
• •Excellent analytical and problem-solving skills
• •Strong understanding of instruction-set architectures
• •Knowledge of Cadence JasperGold and VManager
• •5+ years of experience in the semiconductor industry
• •Proven track record in verifying complex designs
• •Skilled in trade-offs between quality and schedule
• •Familiarity with SerDes and high-level protocols
• •Delivered reusable and optimized formal models
• •Bachelor of Engineering in Electronics and Electrical Engineering

Aufgaben

• •Develop formal verification methodologies and best practices
• •Participate in RTL design reviews
• •Prepare design verification plans based on specifications
• •Document results and coverage metrics for formal sign-off
• •Plan and schedule projects for timely completion
• •Maintain the design verification environment
• •Track and close design bugs
• •Collaborate with RTL design engineers to create formal micro-architecture specifications
• •Deliver reusable and optimized formal models and verification codebases

Tools & Technologien